Research On LDPC Codes Applied To NAND Flash

In today's big data era,massive amounts of data need to be stored.NAND Flash is widely used in electronics,medical,automotive,industrial and other fields due to its high capacity,low power consumption and good performance.However,with the improvement of semiconductor technology level and the increase of data stored in NAND Flash memory cells,the original memory error rate of NAND Flash has increased significantly.The error correction codes such as RS and BCH can no longer meet the requirements of NAND Flash for error correction performance.At this time,the LDPC code with the performance close to Shannon becomes the error correction code of NAND Flash.In this context,it is of great significance to design a high-performance error correction module that meets the requirements of NAND Flash.This paper first analyzes the storage error principle of NAND Flash.Considering the quasicyclic nature of the QC-LDPC code,the complexity of the codec can be reduced,and the codec can be implemented on the hardware.Therefore,the LDPC code is used to construct the LDPC code for NAND Flash using the PEG construction method combined with the QC-LDPC code.Then,according to the structure of H check matrix,the encoding and decoding algorithm is improved.For the decoding algorithm,the BFLMS algorithm based on bit flip algorithm and layered minimum sum algorithm is proposed.It can perform fast decoding iteration while maintaining good error correction performance,meeting the requirements of NAND Flash for speed.Then,the corresponding hardware structure of the codec is given,and the hardware structure of the decoder with adjustable parallelism is described in detail.The codec circuit is designed using the Chisel hardware language.According to the input H matrix parameters,the Chisel code can generate the corresponding codec circuit with great flexibility.Finally,the UVM verification platform is built to simulate and verify the RTL circuit of the codec.Then the FPGA board level test and comprehensive simulation are performed on the codec circuit,and the results of verification and test are analyzed and compared.The test results show that the error correction performance of the codec designed in this paper is good.When RBER is equal to 31.45 10-?,the UBER can be made 1015-or less,which can meet the actual demand.The analog integrated circuit shows that while using 90 nm CMOS technology,the throughput rate has reached 9.872 Gbps,and the throughput-to-area ratio has reached 1.705Gbps/2mm.Therefore,the codec module designed in this paper has certain practical value in NAND Flash.