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Research On The MLC Nand Flash Error Control Technology Based On Nonbinary LDPC Codes

Posted on:2017-08-06Degree:MasterType:Thesis
Country:ChinaCandidate:C Y LiuFull Text:PDF
GTID:2348330482486872Subject:Electronics and Communications Engineering
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Digital storage is an emerging high-tech industry.As the representative of high-density storage technology,the rapid development of Nand Flash memory technology has caused several rounds of revolutionary upgrading.With advantages of simple structure,reading and writing speeds,high stability,energy-efficient,Nand Flash memorys become increasing important and mainstream applications in storage field.With the continuous upgrading of manufacturing technology,original single-level cell memory technology has progressed to multi-level cell memory technology which has greater storage density.In recent years,storage density has expanded more than twice.However,with the continuously increasing of storage density,there are also presents new challenges,especially the increasing probability of error.It is expected that BCH codes and RS codes will not meet the needs of Nand flash error control in the next few years,so we need to look for more powerful error correction algorithms.Low density parity check codes have received intensive research for their excellent properties of approaching Shannon limit,and can be applied to Nand Flash error control field.Some scholars have researched error control technology of Nand Flash based on binary LDPC.However,in general case,compared to non-binary codes,the binary LDPC codes applied to Nand Flash error control are usually very long,and the error correction performance is poor.Although non-binary LDPC codes have many advantages,the encoding and decoding algorithms are too complex,thus looking for good performance and lower complexity encoding and decoding algorithms are very important.This thesis focuses on the research of encoding and decoding algorithms for non-binary LDPC codes,and constructs series of non-binary LDPC codes using in error correct for the MLC Nand Flash.This thesis is organized as follows.First,briefly describes the structural features and basic operations of Nand Flash memory.Then expounds the fundamental principles,especially the encoding and decoding theory of LDPC codes.And using a structural method which can eliminate circle-4 and fast encoding constructs a series of non-binary QC LDPC codes which have high code rates,non-circle-4 and can fast encoding.At the same time,this thesis proposes a high-efficiency decoding algorithm which has good performance.And its computational complexity is much lower than soft decision algorithms.This new decoding algorithm is named as Average Probability and Stopping Criterion Weighted Symbol Flipping decoding algorithm or normal for APSCWSF algorithm.The algorithm puts the average probability of all the information nodes adjacent to the check node as weights to make the flipping-function more effectively and improve the efficiency of the flipping-symbols,and then improves the decoding performance.Atthe same time,the algorithm adds a stopping criterion controlling decoding iterations to further improve the decoding speed.Finally,by simulation and the result analysis,it fully verifies the possibility and superiority of those QC LDPC codes,encoding and decoding algorithms which are proposed in this thesis in the field of MLC Nand Flash error-correcting.
Keywords/Search Tags:MLC Nand Flash, Error checking and correcting, Non-binary LDPC codes, Quasi-Cyclic LDPC codes, Average probability, Stopping criterion, Weighted symbol flipping
PDF Full Text Request
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