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Study On LDPC Codes For NAND Flash Memory

Posted on:2014-09-14Degree:MasterType:Thesis
Country:ChinaCandidate:F Y LiFull Text:PDF
GTID:2268330401459325Subject:Microelectronics and Solid State Electronics
Abstract/Summary:
NAND flash memory is now widely adopted in electronic products. However, NANDflash is prone to bit errors. Especially as the process technology scales down and the adoptionof MLC (Multi-Level Cell) architecture, the storage density of NAND flash increasessignificantly, which leads to a sharp rise of error rate. How to improve reliability and decreasethe high error bit rate become a research hotspot. Low-density parity-check(LDPC) codesis starting to be used for NAND flash because of their excellent performance and superiorerror correcting capability. Since NAND flash asks for large capacity, low error rate, and lowcost, it needs high-rate and long LDPC codes with high performance and low complexity. Theneed of high-speed data transmission of NAND flash also demands fast encoding of LDPCcodes. Therefore it has great practical significance to apply LDPC codes to NAND flash byconstructing high-rate and high-performance LDPC codes which can be encoded quickly anddesigning decoding algorithm with rapid convergence and low complexity.This thesis studied construction of LDPC codes for NAND flash memory. A constructionof QC-LDPC codes which can be encoded quickly with high performance was developed. Inthis method, the right part of the check matrix was constructed to be a quasi double diagonalstructure, so that the LDPC codes could be encoded quickly. While constructing the left partof the check matrix, a cycle elimination algorithm with optimized computation was proposedto eliminate cycle-6efficiently, reducing large computation for high-rate and long-code LDPCcodes significantly. Simulation result showed that, compared to the existing(69615,66897)EG-LDPC codes for NAND flash,(34085,32481)LDPC codes constructed bythe proposed construction yielded a performance gain of about0.5dB by shorter code length.In respect of decoding algorithm, an improved shuffled BP algorithm(ISBP) bymodifying nodes iteration was developed. The algorithm could improve performance andreduce computation amount compared to SBP algorithm. It also raised the convergence speedand decreased half number of iteration of BP algorithm. Then an improved shuffled Min-Sumdecoding algorithm was proposed by combining the ISBP and Normalized Min-Sum decodingalgorithm. The scheme had the advantages of fast convergence and good performance of ISBP algorithm, as well as the advantage of low computation complexity of NMS algorithm, whichwere verified by simulation result.
Keywords/Search Tags:NAND flash, Quasi-Cyclic LDPC codes, ECC codes, SBP algorithm
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