NAND Flash Memory ECC Based On LDPC

With the development of the Internet of Things,storage technologies are changing.Because of NAND Flash has high storage density,low cost,fast erase and write data,it is widely used in various electronic products.However,with the advancement of semiconductor process technology and the rise of multi-level memory technology,the original bit error rate based on NAND Flash storage has risen directly to the 10-3 magnitude.The performance of ECC on traditional BCH codes cannot meet the requirements of high storage density electronic products,so with high performance of ECC at high bit rates on LDPC have become focus of research.In this paper,NAND Flash storage is used as the application background,and the error correction algorithm based on LDPC code is completed.The encoder and decoder module circuits are designed and implemented in engineering.The paper describes the basic structure of NAND Flash and the principle of flash storage.The NAND Flash error mechanism analysis is carried out,and it is concluded that the QC-LDPC code is suitable as the application error correction code of NAND Flash.In addition,the check matrix construction method is also analyzed in current.Considering the practical application of the project,obtain the check matrix with the PEG construction method.The traditional normalization min sum algorithm parallel information transmission structure is changed into the layered message transmission structure,and then combined with the idea of bit flipping algorithm,the RLMS algorithm is proposed.The simulation results show that the algorithm has a high convergence speed,and the average number of iterations is reduced by about 31.7%-34.4%,and have a good decoding performance.In order to meet the requirements of error correction module,this paper proposes a semi-parallel decoder architecture,which implements the RLMS algorithm and supports H matrix online programming.According to the mathematical characteristics of the constructed check matrix,a simple and fast coding method is proposed.In order to cooperate with the decoder,an LDPC encoder with a resemble CPU architecture is designed,and Shifter module circuit is optimized.Finally,the encoding algorithm of this paper is realized.The simulation environment of Matlab and ModelSim is established,and the error correction module of LDPC code is simulated by software.Based on Xilinx's XC7K325T board and Flash module,the LDPC code error correction module is verified by FPGA.The experimental report shows that the performance of the error correction code module designed by this paper has 4.15×10-3 RBER.Supporting the transformation of QC-LDPC codes,and in this paper,different Quasi-Cyclic LDPC can be constructed and used in the circuit modules.After synthesize,the decoder circuit can achieve a throughput of 9.52 Gb/s.Compare with the NMS algorithm,the hardware memory required of the RLMS algorithm is only increased by 0.55%.