Research On ESD Protection Based On SCR Structure

As a common natural phenomenon,electrostatic discharge has a serious effect on the reliability of the chip.The feature size of devices is decreasing and the integration of chips is also improving with the the development of semiconductor technology,thus this puts more stringent requirements on the ESD research of the device.Smaller ESD windows are needed especially from the perspective of robustness of ESD devices.In this paper,the basic principles of ESD protection are briefly introduced.The index requirements of ESD research are given according to the ESD design window.Then the working principles of the basic ESD structures used commonly under ESD stress are discussed in detail.On this basis,the traditional SCR-LDMOS structure and SCR structure are analyzed and compared in detail,then the existing problems are improved.(1)To improve the shortcomings of conventional SCR-LDMOS device,such as high triggering voltage and low holding voltage,a new ESD protection device embedded with P area SCR-LDMOS is designed and proposed in this paper.By introducing the new avalanche breakdown point,the internal parasitic transistor can be able to turn on faster,so as to reduce the trigger voltage of the device.And this device introduces a new parasitic transistor that can clamp positive feedback in the structure,so as to increase the holding voltage.The MEDICI simulation results show that the trigger voltage of the new structure is reduced by 58.45% and the holding voltage is increased by 13.4V compared with the traditional structure,(2)Using the idea of introducing the external current source to trigger the SCR device in the substrate triggered SCR structure,a new structure of external PMOS triggered SCR device is also proposed.The structure uses PMOS to replace the reverse PN junction and thus reduce the trigger voltage of the device.Then a SCR device triggered by PMOS and clamping the internal voltage is improved and proposed.The new structure utilizes PMOS to trigger SCR structure,the trigger voltage is reduced.At the same time the new parasitic transistor is used to clamp the internal voltage,then the positive feedback effect can be suppressed and increase the holding voltage.The simulation results show that the trigger voltage of the new structure is reduced by 32.39% and the holding voltage is increased by 13.88 V compared with the traditional structure.