Optimization And Verification For BOOM Processor Based On RISC-V Instruction Set

BOOM(Berkeley Out-of-Order Machine),which is developed based on the RISC-V instruction set architecture by the University of California at Berkeley,is an open source processor which is mainly used for ASIC optimization and FPGA.A solution for timing optimization of the processor is proposed,which is used to improve the overall running speed of the processor,based on a research of the implementation of the processor micro-architecture and combining the critical path of the comprehensive report.At the same time,a simulation verification test bench for the verification of processor is built.Firstly,the pipeline micro-architecture of BOOM processor and synthesized the processor using Synopsys' s Design Compiler tool under SMIC 40 nm process library are researched.After that,timing optimization in three pipeline levels,which contains instruction decoding,register renaming and instruction transmitting,according to the critical path of synthesized results report are performed.By cutting the pipeline and optimizing the internal logic,the speed of the processor is increased and the logic synthesis frequency increased by 14.2%under the premise of increasing a certain number of clock cycles.Secondly,a verification strategy for the instruction set simulator and RTL co-simulation to verify the function of the BOOM processor is proposed.At the same time,in order to ensure the correctness of floating-point execution unit function and make up for the defects of instruction set simulator,a verification platform based on Universal Verification Methodology(UVM)is built for floating-point execution unit of BOOM processor to verify all floating-point instructions supported by floating-point unit,and then the floating-point verification platform is integrated into the BOOM processor verification platform for processor verification.In order to verify FPU unit more effectively and quickly,a verification testbench is built using the popular universal verification methodology and SystemVerilog language and the reference model is used to compare the results of the DUT combined with code coverage and function coverage to ensure the correctness and completeness of the verification.The final code coverage is reached 98%and the functional coverage is reached 100%,which means that the verification of FPU is completed.Finally,the results of instruction execution in BOOM processors are compared at the architecture level by integrating FPU verification platform.A processor verification platform with full functions of automatic comparison between ISS and RTL simulation logs and automatic coverage collection is realized.The random instruction generation platform adopted can effectively accelerate the convergence of coverage.The final code coverage is reached 93% and the functional coverage is reached 100%.At the same time,the uncovered code in RTL transformed by Chisel is analyzed.Up to now,there are no obvious abnormalities in the BOOM processor release test after optimization of pipeline and verification.The processor has started the operating system independently on the development board of the FPGA,and it can run more than 30fixed-point and floating-point test programs separately.Finally,the optimization and verification of the BOOM processor have been completed.