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Implementation Of Automatic Verification Of Processor Based On UVM

Posted on:2022-09-08Degree:MasterType:Thesis
Country:ChinaCandidate:M J ZengFull Text:PDF
GTID:2518306731476764Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
In recent years,the development of integrated circuit has become a symbol of the national scientific and technological strength.With the arrival of 5G era,the demand for the prosperity and development of the integrated circuit industry has been on the way,the importance of verification work is self-evident.The work of this thesis originates from the 8-bit MCU project of the internship company.The author is responsible for the verification of its self-developed processor,and mainly verifies its instruction set,the function and characteristics of the processor.The author collected the previous related articles and studies of processor verification,found that the current verification method of processor has always been simulation,assertion and waveform positioning.They usually just verify this instruction set,but pay litter attention to the combination of instruction and some other functions and characteristics of the processor.This thesis attaches importance on the various aspects of validation.The verification is mainly divided into two levels,the chip system level verification and the processor module level verification,validation of the specific content is as follows:(1)Processor system level verification is carrying on the MCU system level verification platform,and use the platform to simulate the processor according to the direct verification point.The system level verification platform transcodes the content of the instruction file to program storage.After the start of verification platform,the processor takes the instruction from the program memory and control the chip.The program cases achieve the effect of validation by "self-checking",and interacts with the monitor of the verification platform by writing values in registers to signal the success or failure of validation.(2)In the processor module level verification,we write each component of the verification platform and simple model of the memory by System Verilog,and build a module level verification platform based on UVM validation methodology,which mainly includes monitor,agent,transaction,reference model,scoreboard,coverage model,program memory,data memory,etc.The consistency between the processor and the reference model is compared by simulation method,and random cases are constructed to verify the random combination of instructions.Based on code coverage and functional coverage statistics,validation target of the processor is successfully completed,coverage has reached 100%.The system level directional verification and the module level random verification share out the work and cooperate with one another,complement each other,and make validation for the processor satisfactory answers.The company MCU chip has been taped out successfully,and the processor function is normal.In this thesis,the method of program "self-check" has a certain innovation significance,and the idea of division labor combination verification can provide some new directions for chip verification work,which contains processor system level function verification and module level instruction random verification.
Keywords/Search Tags:Processor Verification, UVM, System-level verification, Module-level verification, Program self-inspection
PDF Full Text Request
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