| Register is very important in sequential circuit.The development of register's per-formance and energy plays an important role in the design of total circuit.In order to de-sign the circuit with high performance and low power consumption,It is very important to make an optimization of register's performance and energy.Aiming at different demands,we optimize the standard cell register in delay, power and areas under 0.13μm CMOS technology,and establish a high performance standard cell register library.We use double edge trigger technique to optimize SDFF, the LSDFF after optimized achieves 18% rise in speed,30% fall in energy and 36% fall in power delay product(PDP),we use clock gate technique to optimize TGFF,the GTGFF after optimized reaches 35% fall in energy. Although the speed has a weak degradation,the PDP has improved greatly.We use conditional discharge technique to optimize HLFF,the CDFF after optimized is 35% rise in power ,the speed also have a weak advance. SMDFF is a scan flip-flop use lssd structure,its speed is 52.06ps,its power is only 87.3μw,its structure is simple and its transistor's amount is small,its delay and power is better than register having not scan function.the optimization method makes a matting for developing flip-flop of higher performance. |
