Design Of All Digital Phase Lock Loop For USB/Ethernet

At present,serial communication interface technology is widely used.As a module to provide clock signal for interface circuit,the performance of PLL directly affects the overall performance of interface circuit.Analog phase lock loop(APLL)is used in traditional interface circuits,in which the low-pass filter is composed of passive devices,but passive devices usually consume a large area,which is not conducive to reducing costs.Moreover,the compatibility between analog PLL and the current mainstream digital integrated circuit technology is also a problem.To solve these problems,an All Digital Phase Lock Loop(ADPLL)is proposed.ADPLL does not need to use analog filters,which can effectively save area.In addition,ADPLL has good compatibility with the current mainstream digital circuit technology.This topic comes from the actual project in the enterprise.Based on TSMC22 ULP technology,an ADPLL system suitable for USB2/Ethernet application is designed.In the design,according to the TOP-DOWN design process,the system is modeled firstly,and the noise source in the circuit is analyzed by analogy,and the phase domain noise model is established.The circuit structure is determined and the circuit parameters are calculated by using the model.The designed circuit is mainly divided into two parts,the main circuit of PLL and the power supply circuit.The main circuit of PLL consists of Time to Digital Converter(TDC),Digital Loop Filter(DLF),Digital Control Oscullator(DCO)and MultiMode Divider(MMD).In the design of TDC,single delay chain structure is adopted to reduce area consumption and power consumption;DLF restrains noise;DCO combines current control coarse tuning with voltage control fine tuning to improve control accuracy and reduce quantization noise;MMD uses cascade structure of dividing frequency units to avoid the non-linear problem of traditional structure,while improving the reusability of the circuit.The power supply circuit consists of a reference voltage source and two Low Dropout Regulators(LDO).The reference voltage source generates a low noise reference voltage in the form of current injection resistance and is calibrated by an automatic calibration circuit.The two LDOs supply power to TDC and DCO respectively.The folded cascode operational amplifier is used as error amplifier for TDC power supply,and the Miller effect is used to compensate for the lower static current and smaller area consumption.The LDO for DCO power supply uses the flipped source follower structure,which separates the error amplifier from the regulating loop to achieve very low output noise and ensure the numerical control oscillation.Make sure the circuit works well.Finally,the layout are drew and post-simulation are carried out.The simulation results show that the ADPLL designed in this paper can meet the application requirements.The simulation is carried out at TT 60 degree.The total power consumption is 2.3 mW,the phase noise is-94 dBc/Hz@1MHz,and Peak to Peak Jitter is 53 ps.LDO output noise for DCO is 16nV?Hz@100kHz,power supply suppression is-47dB@1MHz,static current is 320?A.LDO output noise for TDC is 49nV/ ?Hz @100kHz,power supply suppression is-45dB@1MHz,static current is 50 ?A.