A 14bit 125M SPS CMOS D/A Converter

Nowadays, digital to analog converter (DAC) plays a very important role in the modern digital and analog circuit and has become one of the factors, which restricts the development of the computer, communication and DSP. It creates a great demand for high speed and high precision. Presently, the trend toward high speed high resolution and embedded DAC has been seen as the most interested two directions in abroad, which are just the two deficiencies in our country.In this dissertation, a 125M SPS 14bit DAC is presented, which is based on 0.25μm Mixed-Signal CMOS process. In this design, DAC architectures are analyzed and different decode modes are compared. A 5+4+5 segmented decode using current-steering architecture, which has advantages of both binary decode and thermometer decode is presented. This DAC is composed of several part circuits as follows: A bandgap reference circuit, which has a low temperature coefficient and a high power supply rejection ratio, is used to give a constant reference. Resistors with different temperature coefficient are used for curvature compensation in this circuit. A low voltage cascaded current mirror bias circuit that can provide an exact and steady bias voltage for current array is used. In design of a high impedance current cell and differential current switch, dummy switches are used and a switch-current driver circuit is proposed for reducing the effect of clock feed through and glitch current. Several digital circuits are also used in the proposed DAC to implement such as flip-latch circuit, thermometer decoder, current select circuit, etc.The whole circuit is realized in TSMC0.25μm Mixed-Signal SALICIDE(2P5M or 1P5M+, 2.5V/3.3V) process. Cadence simulation shows that it can work well to meet the requirements.