The Design Of External Capacitor-Less CMOS Low Drop-Out Voltage Regulator

The rapid development of information industry such as computer and communication is pushing towards complete system-on-chip design that includes power management. The study of power management techniques has increased spectacularly these years corresponding to a vast use of potable devices supported by batteries. The main purpose of power management is to improve the device's power efficiency resulting in prolonged battery life and operating time of device. It contains several subsystems, including linear regulators, switching regulators, control logic and so on. Low drop-out voltage regulator is an essential part of power management that can provide constant voltage supply. Its main advantages are relatively simple circuit, low power, small output ripple, no electromagnetic interference, high power supply rejection ratio and so on.The conventional LDO voltage regulator, for the stability and transient response requirements, needs a relatively large output capacitor in the range of several microfarads, which cannot be realized on chip in current design technology, thus LDO requires an external pin for the output capacitor on PCB. But considering the SoC design cost, system robust, final board resource and so on, it really demands a high performance external capacitor-less LDO. Several topologies have been proposed, however they are unstable at low load, which makes them not suitable for the real applications. The dissertation proposes a new external capacitor-less LDO topology that combines transient enhancement network and pole-splitting network. The main content is as follows:Chapter one introduces power management techniques and the characteristics and applications of LDO briefly and then focuses on the development and recent research of external capacitor-less LDO. In chapter two, the basic principle of LDO is presented. The main characteristics of LDO including static-state specifications, dynamic-state specifications, high frequency specifications and efficiency are introduced. At last it points out the key and difficulty of external capacitor-less LDO design through general analysis.The third chapter provides the system analysis and design of external capacitor-less LDO. First it analyzes the stability and transient response of uncompensated system, and then according to these problems and several other tradeoffs needed to be considered in real design, a topology which combines transient enhancement network and pole-splitting network is proposed. The principle of transient enhancement network is to sample the change of output voltage using pseudo differentiator, transform it into current and charge the gate of pass transistor efficiently meanwhile the pole-splitting network based on nested Miller compensation is used to ensure the stability for the full load. Then the advantages of proposed topology are analyzed and several considerations during circuit design are pointed out.Chapter four fulfills the transistor level design of proposed structure. The prototype circuit is composed of bandgap voltage reference and LDO main circuit. The bandgap reference uses resistors of different temperature characters to compensate the high order term and also a technique which can enhance the power supply rejection ratio is adopted to provide constant reference voltage. The LDO main circuit is designed according to the requirements obtained from the system analysis and other tradeoffs needed to be considered in analog circuit design. Pre-simulation, layout design and post-simulation are finished using CSMC 0.5um DPTM mixed signal CMOS process under Cadence IC design integrated development environment. The final results show that the designed external capacitor-less LDO can operate stably for the full load ranged from 0.5mA to 50mA. The maximum output overshot and undershot are less than 115mV and the settling time is about 3.5us during the load transient. During the supply voltage transient, they are 500mV and 5us respectively. The PSRR of the proposed circuit is larger than 50dB at the frequency of 1 kHz and still less than 25dB at 100 kHz.The last chapter summaries the whole work of the dissertation.The performance of proposed external capacitor-less LDO can meet most application requirements and occupy less chip area. It can be an attractive solution for the full on chip power management. Meanwhile the topology and design methodology proposed in the dissertation have universality. Different products can be designed quickly according to different specifications using the proposed methodology, which makes it suitable for the real applications.