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Design Of 14-Bits SAR ADC Circuit

Posted on:2022-03-08Degree:MasterType:Thesis
Country:ChinaCandidate:Y X ZhangFull Text:PDF
GTID:2518306572966169Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
With the rapid popularization of Internet technology and digital communication equipment,digital signal processing and related technologies have developed rapidly in recent years.Analog to digital converter(ADC),as the communication bridge between analog signal digital signal,plays a significant role in realizing the conversion of analog into digital signal with high speed and strong anti-interference.At present,after comparing other mainstream ADC architectures,successive approximation ADC(SAR ADC)has the advantages of simple structure,medium speed,medium precision and low power consumption.They are widely used in portable products,video transmission,wireless sensor network,and industrial control other fields.SAR ADC has become a hot spot of ADC research and it has received extensive attention in recent years.Based on the above background,a 14-bit SAR ADC of high precision and low power consumption has designed in this paper.The SAR ADC is designed which includes a reference voltage module,a comparator module,a digital to analog converter(DAC)module and a digital logic control module in this paper.The bandgap reference with low-temperature coefficient and high-precision is proposed by using the temperature piecewise compensation and digital trimming technology.The bandgap reference output voltage is boosted by the error amplifier as the reference voltage of the SAR ADC.A high-precision comparator is designed with the structure of an open-loop comparator and a reproducible comparator.A segmented capacitor array is used in the DAC which can improve the conversion speed and accuracy.And,a capacitor series-parallel structure is used in the low-level capacitor array to reduce the chip area effectively.The Verilog language is used to achieve the successive approximation in the digital logic control module.The internal clock circuit is designed to provide the clock signal for the comparator module.The SAR ADC is simulated and the layout is drawn based on HHGRACE 0.11?m CMOS process.Simulation result shows that the bandgap reference achieves temperature coefficient of 2.18ppm/°C from-40°C to 125°C.Bandgap reference output voltage is 1.2V with in the error of ±5m V under 3.3V power supply voltage.The reference circuit output voltage is 2.4V.The comparator module achieves a precision of 4?V and a power consumption of 1.667 m W under normal operation.The post-simulation result of the overall SAR ADC is: SNR,SNDR,SFDR and THD are68.75 d B 66.28 d B 70.75 d B and 69.91 d B respectively.The ENOB is 10.72 bit,when a clock frequency is 18 MHz,a sine signal with a sampling frequency of 900 k Hz,an input signal frequency of 385 Hz with the amplitude of 2.4V.The power consumption of SAR ADC is 3.696 m W in normal work.The results show that the 14-bit SAR ADC can achieve the design requirements.
Keywords/Search Tags:SAR ADC, bandgap reference, comparators, segmented capacitor structure
PDF Full Text Request
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