An Integral Nonlinearity Error Calibration Algorithm For Analog-to-Digital Converters Based On QHCF Modeling

With the chip preparation process of continuous improvement,analog-to-digital converter(Analog-to-Digital Converter ADC)the sampling precision and speed have been improved,at the same time,the nonlinear integral error also becomes more and more obvious.Therefore,under the condition of the existing ADC chip,how to further improve the performance of the data acquisition equipment becomes an urgent problem to be solved.Pure use of technology to achieve high speed and high precision ADC more difficult,and through the digital back end compensation method to eliminate the ADC integral nonlinear error has received more and more attention.Among many errors of ADC chip,the integral nonlinearity error is the most critical and most difficult to calibrate.In order to solve the difficult problem of ADC integral nonlinear error calibration,this paper deeply studies the ADC integral nonlinear error model and calibration algorithm,and the main work is as follows:In chapter ?,the shortcomings of the existing ADC integral nonlinear error model and calibration algorithm are analyzed.Firstly,this paper introduces the origin and characteristics of ADC's differential nonlinear error and integral nonlinear error,and makes a research on the reason of nonlinear error;Then,the existing problems of the ADC integral nonlinear error polynomial model and the Volterra series model are analyzed;Finally,the shortcomings of the existing ADC integral nonlinear error calibration algorithm are analyzed,Including ADC integral nonlinear error LMS adaptive calibration algorithm and Volterra series model based on ADC integral nonlinear error calibration algorithm.The analysis results can provide reference for the design of ADC integral nonlinear error calibration algorithm in this paper.In chapter ?,the shortcomings of ADC integral nonlinear error calibration algorithm are improved,and an algorithm based on QHCF(Quadratic High Component Frequency)ADC integral nonlinear error calibration algorithm.Firstly,a ADC integral nonlinear error model is designed,and the parameters of the model are given.By using this model,the integral nonlinear error of ADC is represented,and the fitting degree of different models are analyzed;Then,a ADC integral nonlinear error calibration algorithm based on QHCF model is proposed.This calibration algorithm consists of two processing procedures,the foreground error estimation and the background digital compensation.Among them,the structure of the estimation algorithm,the method of selecting the training signal and the selection of the number of the fitting function segments are given in the foreground error estimation algorithm.In digital background compensation algorithm,the reconstruction method of the error signal and the method of eliminating the error signal are presented;Finally,according to the complexity of the error calibration algorithm proposed in this paper,the error calibration algorithm and the complexity of the existing calibration algorithm are compared.In chapter ?,the simulation and verification of the ADC integral nonlinear error calibration algorithm based on QHCF model is proposed.The system performance,calibration time,resource consumption and calibration speed of different calibration algorithms are compared and analyzed.The hardware resource consumption of the calibration algorithm is verified by hardware simulation.The simulation results show that the spurious free dynamic range for calibration of ADC increased from 84.6dB to calibration before calibration after 100.8dB,SINAD increased from 66.4dB to before calibration after calibration of 66.6dB,effective from calibration before the 10.71 bit increased to 10.75 bit after calibration.The research work in this paper provides a certain research foundation for improving the performance of pipelined ADC and the integration of the integrated nonlinear error calibration algorithm,which is expected to be applicable to all pipeline ADC calibration.