Research On High-speed Large-capacity Memory Access And Management Technology Based On Flash Memory Array

Today's space exploration and ground monitoring have become the focus of attention of all countries in the world.In order to cope with the increasing number of single space exploration missions,the observation equipment that space vehicles need to carry has also increased.These observing devices will generate huge amounts of data,and their speed requirements will become higher and higher.Therefore,high-speed large-capacity memory has become an extremely important link in the star-to-ground transmission chain.For the mainstream solution of high-speed large-capacity memory today,NAND Flash array,this article mainly studies and deals with the following three issues:?1?How to design the access method of the flash memory array to meet the speed requirements while minimizing the array area?In terms of throughput limitations,the main problem lies in the page programming time for write operations.In the industry,pipelines are usually used to eliminate the waiting for page programming time,but pipelines are generally set between storage particles.In this way,only the number of chips is increased to meet the throughput rate.In this regard,this article uses the combination of on-chip water flow and inter-chip water flow,so that the array area is maximized and reduced while satisfying the throughput and capacity;?2?How to improve the management technology of flash memory array to achieve efficient utilization and scheduling of storage space while ensuring throughput rate?Traditional solutions all use the operating system as the core file management.This method has strong flexibility,but the operating system will cause a great restriction on the throughput of the array.This article uses a hardware file management solution implemented entirely by FPGA,which achieves efficient management of storage space without hindering the improvement of throughput rate;?3?How to ensure the accuracy of data input and output under the condition of super high throughput?Generally,the serial coding and decoding method of BCH code or RS code is used in the scenario of lower throughput rate,which consumes more clock.This article uses the FPGA-based BCH parallel encoding and decoding method,which greatly reduces the impact of encoding on the throughput rate and makes the bit error rate better than 1×10^-10.The above designs have been verified by behavior-level simulation and board-level verification,confirming the feasibility of the design.