Design Of High-speed Large-capacity Memory

With the development of space astronomy technique and the dramatically growth of data output bandwidth, human beings are getting more and more interested in the study of the speed, capacity, power consumption and reliability of the information storage array. How to store the super-speed and mass information growing out of the production practice in an effective way is the new requirement that the storage technology should meet. The solid-state memory in feature of nonvolatile and storage density has been widely used in many fields. Therefore, how to access the data in time and manage the information more efficiently and conveniently is the key point of this paper.The thesis gives the background of the research and the developments of the related technology firstly in view of macroscopic perspective. Secondly, it represents the design of hardware and the structure of the software.And then this thesis gives the hardware design of the system, and describes the communication protocols between control module and the host computer,and the storage module, and the anolog module;and the the communication protocol between internal DSP and FPGA of control module. A reliable transmission module, which realizes the parallel extended pipeline processing and the Serial to Parallel conversion of300MB/s high speed data, are designed and implemented in the controller.This thesis chooses the Sequential Storage Model. Through the Block Address Mapping Table, ENFFS realizes the management of bad block addresses and address mapping. Meanwhile, every function module is based on the File Node Table. The conspicuous feather of the model is that every file is saved from the low address and the free space caused by the file delete or cut cannot be used unless the array reorganization is executed.At last, we list some problems met in the development and their resolutions. Summary and some suggestions are also necessary at the end.