Real-time Error Correction Technology Research For Flash Memory Based On FPGA

As a long life and non-volatile memory, Flash Memory is very popular in the storagearea because of its quick speed in writing and reading and the advantages of keeping datastored in a storage area in the situation of power down. But the growth of themanufancturing process and the high integration of Flash Memory, the bit error ratio is alsorising. The error correction ability of general error correction technology is limited while itcan’t meet the need of current Flash Memmory error correction ability. In view of aboveproblem, the author puts forward that using BCH code algorithm to improve FlashMemory error correction ability according to the domestic and foreign research trends.Simulatin results show that ECC module of BCH code improves the error correction abilityand code efficiency of Flash Memory.This article contains the following aspects:(1) Firstly introduce the development process of BCH algorithm. BCH code is one ofbest linear block codes so far as found. And it’s suitable to correct the random eror of FlashMemory. Based on this, this paper introduces some algebra knowledge of BCH code,including limited domain theory and GF (2m)structure and the characteristics of limiteddomain and elements of the series and the minimum polynomials, etc. Base on theunderstanding of the relevant knowledge of BCH, puts forward BCH code definition. BCHcode is a kind of cyclic code what can correct random errors. The whole BCH codecinclude two part of coding and decoding. The progress of code can get parity polynomialsby generated polynomial, and then get the code polynomial. The progress of decode firstlycalculates syndrome polynomial according to received code polynomial, and then computethe wrong position polynomial, finally get the wrong position through Chien search circuit.(2) After primary understanding of BCH codec, it needs to consider how to design theBCH code from the coding efficiency and error correction ability. In BCH encoding circuit,the main limited factor for coding efficiency is the transmating data width. Because of eachclock processing one bit in serial circuit, the processing efficiency is slow and have no wayto meet real-time demand for error correction. BCH parallel encoding circuit realizes to progress more data in one clock what improving the efficiency of data processing. In BCHdecode circuit, it make its circuit from serial to the parallel which improving the processingpower of a clock through the improvement of syndrome calculation and Chien searchcircuit.(3) It used Verilog HDL language to implement BCH codec circuit. Using BCHencode technology to encoding data which stored in the encoding module. Generatingpolynomial can generate195bits parity, and then stored them to the spare area of FlashMemory. We can get syndrome polynomial and error lacation polynomial using technologyof decode. If it has the wrong bits, then using Chien search to seek error positionpolynomial and check out the wrong position.