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The Design And Research Of Large-capacity Device Based On Nand Flash

Posted on:2016-01-17Degree:MasterType:Thesis
Country:ChinaCandidate:Z L ZhouFull Text:PDF
GTID:2298330467491582Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Nand flash—a non-volatile memory medium, has been widely used in the memorydevices of high speed and low power consumption because of many advantages such as widerrange of temperature, high shock resistance, high reliability, etc. Many films such as modernspace and military equipments highly acquisite all kinds of information, all these need highspeed, large capacity memory devices to cooperate the acquisitions.The paper, firstly, surveyed and Analysis the research backgrounds of the memorydevices, especially the large capacity ones, in the background of the researches anddevelopments of large capacity memory devices at home and abroad, and designed a largecapacity device, according to the actual demand of the multi channels data storage in theprocess of dynamic signal test. The device built a memory array based on signal chip NandFlash, the array is a key of the memory device. Receiving8channels highly LVDS image dataat the input port of the memory device,the data format of single channel image data was:320(Columns)256(Rows)16(bits). The device stored these image data into the flash arrayunder the control of the main control chip—FPGA, aiming at Data transmission in the PFGA,the paper designed the transmission mode—data, to avoid unnecessary loss of time. Aiming atthat the flash chip would not response the other program while the flash was in the process ofprogramming, the paper deigned a time-sharing load storage technology to improve theaverage storage rate. In this paper, the system illustrated the receiving the image by LVDS,data transmission and controlling respectively from the hardware and software to ensure thereliability of the large capacity storage device, the paper focused the BCH error correctingcoding management about the bad block, wearleveling, etc. Because the bad blockmanagement in coding process appeared the problem with the same location about the badblock, the paper designed a bad block table reconstruction technique.The system used altera company’s cyclone III series FPGA to control the whole storagesystem, the clock was50MHz. By analyzing the data acquired from the experiments, thedevice built of the Nand Flash array could record the image data effectively, reliably, andmanaged the bad block effectively, it met the requirements of design, had the very high practical value.
Keywords/Search Tags:Nand Flash, large-capacity, the memory array, bad block coding management, FPGA
PDF Full Text Request
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