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Research On High-speed Data Storage Technology Based On Flash Memory Array

Posted on:2013-01-18Degree:MasterType:Thesis
Country:ChinaCandidate:N J PuFull Text:PDF
GTID:2248330371968620Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
In order to solve the disadvantage of a single chip flash memory’s limited storagecapacity and speed. This article describes the achievement of high speed and large capacitystorage memory, by constructing a flash memory array to increase the storage capacity,improve the storage speed. The use of bit extension technology and time-sharing loadtechnology to complete horizontal and vertical expansion of monolithic NAND FLASHmemory cell, and build a generic m×n array. Then invalid blocks on the storage array isproposed approach, according to the array’s different values of M and N, including totalrelation, fully independent, row relation and column relation four management mechanism.After further study working principle of the array, dedicated DMA logic control circuitdesigned for the storage array. Finally, we discuss the approach to data management of thestorage array. The establishment of the system information area, the station logo area, the fileinformation area, the parameters configuration area and the data storage area can managestorage data conveniently and effectively.After discussing the storage array’s establishment, working principle, invalid blockprocessing mechanisms and methods of data management, the design of a dynamicparameters storage system is been taken for example to introduce the use of storage array. Thestorage system consists of the FPGA control system, the analog to digital converter modules,the FLASH memory array and the USB interface circuit. The control system is a SOPCsystem of FPGA, the SOPC internal integration of the Microblaze soft core processor anduser self-designed IP core, the user logic circuit is used to complete the data acquisition andstorage. The analog to digital converter module supports synchronous data acquisition of 2, 4,8, 16 four selectable channels. If 16 channels simultaneous acquisition, the sampling rate canreach 400ksps. The flash storage array system is a 1×4 array, with row relation invalidblocks’ management mechanism. The main role of the USB interface circuit is a data pathbetween the processor and the computer. Then the storage system can receive the operationcommands conveniently from the computer, and ensure the return of the test data. Thehigh-speed storage characteristic of the storage array is verified by an experiment. Meanwhile,the reliability of the storage system is assured.
Keywords/Search Tags:FLASH memory, storage array, invalid blocks, data management method
PDF Full Text Request
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