Simulation For High Density Flash Memory Channel And Research On Low Complexity Error Correction Method

With the popularity of electronic products,people generate large amounts of data on the Internet and mobile Internet every day.Data has become increasingly important.The future will enter an era of data.For these large amounts of data,devices are required for storage.NAND flash memory is widely used as a non-volatile memory device in the current data storage application.In order to meet the needs of large-capacity data storage,the emergence of multi-level cell(MLC)storage technology broke through the limitations of original single-level cell(SLC)storage technology.MLC storage technology improves the storage density of NAND flash by storing multiple bit information in a single flash memory cell.However,the manufacturing process continues to shrink the NAND flash memory chip size,resulting in the cell-to-cell interference(CCI)becomes more and more serious,which has become the impact of NAND flash memory storage of the main factors.In addition,there are other noise in the storage process and the impact of NAND flash memory life.These disturbances can cause errors in the data storage and reading process.Increasing the storage reliability of high-density NAND flash memory has been an important direction of storage research.Using an appropriate error correction code pattern and an efficient decoding algorithm is the common error correction methods.The encoding operation is performed before the information is written to the flash memory block and the decoding operation is performed after the information is read.At last,the original information is restored.By this way,it improves the storage reliability.In addition,the signal processing method is another new way to improve storage reliability,such as the pre-processing and post-compensation signal processing method for threshold voltage signal in NAND flash memory.In this paper,the high density NAND flash channel is analyzed and simulated deeply,and the research on low complexity error correction method is carried out.The specific work can be described as follows:(1)Based on the structure of high-density NAND flash memory,the principle of read and write operation and the characteristics of noise,a high-density NAND flash memory channel simulation model is established.Based on this channel model,it is convenient to study the error correction technology of high density NAND flash memory.By setting the channel parameters and interference factors in the channel model,we can observe the performance of the error correction method in high-density NAND flash memory,and design an effective error correction method.(2)In the error control coding,low-density parity-check(LDPC)codes with high error-correcting performance are adopted as the error control codes for high-density NAND flash memory.Combining with characteristics of the high-density flash memory channels,a modified soft reliability-based iterative majority-logic decoding(modified SRBI-MLGD,MSRBI-MLGD)algorithm is proposed to improve the reliability of the information storage.This algorithm can reduce the decoding complexity while maintain the better error correction performance.(3)In the direction of signal processing,a low-latency post-compensation(LL-Post-comp)signal processing method is proposed.The bit information of the NAND flash memory cell is actually represented by the threshold voltage of the flash memory cell.When the interference occurs,the threshold voltage of the NAND flash memory cell will be changed,resulting in bit information error.The post-compensation signal processing method can compensate the threshold voltage of the victim flash cell.This method improves the storage reliability while generates the lower detection latency.