A Kind Of Design And Verification Of Dynamic Power Scaling System

Since John Bard,Bradton and Shawley of Bell Labs invented the world's first transistor in 1947,our life has had inextricably relationship with chips.From the control unit of electric lights to the CPU,integrated circuit has been promoting the progress of human civilization since the beginning.Nowadays our daily life has been dominated by wearable and mobile devices,so that chips have become necessity as electricity.Meanwhile,with the higher and higher requirement for the performance of mobile devices,it makes researchers have more and more increasingly requirements for chip computing power,power consumption optimization,and even chip technology,which also promote the progress of Integrated circuit.With the increasing complexity of integrated circuit design,both the cost of design and difficulty are also increasing year by year.The mobile device which is as the most frequently used equipment,its baseband chip is the most important and complicated,and the power consumption also directly affects the competitiveness of the product.Therefore,the problem of the power consumption has already become the foremost consideration of a product increasingly,in the meanwhile,it also restricts the development of baseband chip.This paper focuses on the ARC subsystem which is embedded in one of Intel's baseband chip.The ARC subsystem which is a new set of 32-bit quad-core processors embedded into baseband chip for more efficient control of underlying modules,is used for system control and data processing.The reduction of the power consumption is helpful to optimize the power of the whole baseband chip.The dynamic power scaling system is designed to optimize and reduce the power consumption of the ARC system,and it makes the ARC subsystem work under a suitable frequency and voltage matching its load.Thus the dynamic power scaling system aims to optimize its power consumption by adjusting and optimizing the clock frequency and the module supply voltage.This paper implements directional verification of dynamic power scaling system via directed test cases based on C.At the same time,by means of setting up a verification environment based on Universal Verification Methodology(UVM),more randomization will be embedded into the stimulus generation hence covering more corner cases which could have been missing by directed tests.The more randomization verification for dynamic power scaling system achieves,the more complete and convincing our verification will be.In this paper,compared with the previous one,the system power consumption of the ARC processer optimized by dynamic power scaling system reduces by about 35%.Meanwhile,for the dynamic power scaling system,its own power consumption is also reduced by about 56%.In the area of verification,we use different verification environment and test cases to make coverage rate up to 100%,and it make our verification more complete.In conclusion,the design of dynamic power scaling system in this paper has more practical significance.And the optimization of power consumption also makes this baseband chip have lower power consumption and higher product competiveness.