A Study Of Low Power Backend Design Of TD-SCDMA Module Of An Baseband Communication Chip

With the development of semiconductor manufacturing technology, the market for mobile electronic devices has become increasingly demanding. Ultra-deep sub-micron process has been widely used in chip manufacturing and low-power chip design becomes increasingly important. The current low-power design has a corresponding theoretical support and some design techniques, such as dynamic power reduction starting from clock gating, lower static power starting from multi-threshold voltage, power gating, as well as more complex dynamic frequency voltage scaling, etc. However, current chips have large size, various function and high operating frequency, which makes low-power design much more complex. Variety of low-power technology will bring varying degrees of impact on the design itself, requiring the use of low-power method for rational planning of different design requirements.This program comes from a phone baseband chip project of Intel wireless communications technology company, from which the back-end low-power design of TD-SCDMA communication module is completed. Then proposes the idea of a low-power method based on dynamic data path, and explores it in back-end design TD module. This paper studies the power consumption theory of digital circuit, the existing low-power technology and completes low-power back-end design of TD module on the basis of analyzing Unified Power Format(UPF). According to the characteristics of TD module, a reasonable definition of UPF and floorplan are done, and also implements power planning, placement, clock tree and route steps with discussion. Then with this basis, this paper continues in-depth study based on the Dynamic Power Reduction of Data Paths, discusses in detail the theoretical basis of this method and its application method initially identified in the back-end design. By adding Dynamic Power Reduction of Data Paths to the back-end design flow of TD module which is done already, the impact of its back-end chip design phase timing, routing congestion and other content can be explored, as well as the changes in the various steps of the execution time. And the final result can be compared with previous data by power analysis, to determine the validity of data based on dynamic low-power technology path.In this paper, the design uses the Synopsys IC Compiler physical design tools, Prime Time timing analysis tool and Prime Time-PX-power computing tools. TSMC 28 nm process is adopted. In this paper the back-end design of TD module with different flows is also complete. According to the power calculation based on the results, this method makes maximum dynamic power in TD module reduced by about 20% based on the dynamic low-power data path, thus making the total power consumption reduced by 10%. Then impact of the application in the back-end design on timing, routing congestion and implementation time is explored, and no significant design problem is found for TD module. The design that can be used to the actual circuit based on the method of dynamic low-power data path is initially identified. Finally, this paper further discusses the practical effect and the impact of this approach, and a more reasonable prospect of its application methods and conditions...