Low Power Research And Design For Mobile Phone Baseband Chip

High definition display, high processing speed and large memory size are the mostprominent developing areas. Since all of these futures are high power consumed, suchdevices’ standby time meaning the low power mode turns to a more critical problemthan ever. The baseband processor is undoubtedly one of the most importantcomponents for all mobile phone chips. A normal3G baseband processor incorporatesmore than23million gates which makes the power reduction of baseband chip as thekey to reduce the overall power consumption of mobile devices.In consideration of practical applications and communication protocols, this paperproposes a system level low power strategy for baseband chips. The strategy focuses onthe chip level power management based on so-called system FSM and GSM sleep timer.The system FSM switches the GSM system between run state and sleep state andguarantees the system running correctly without system halting, wakeup event missingand so on. When the overall baseband system is running, clock and power supply ofeach subsystem on the chip is strictly timely controlled. The paper describes theprinciple and usage of system FSM in detail. GSM sleep timer is a high accuracyhardware timer and is able to measure integral multiple of TDMA frames with less than1ppm error. In sleep mode, GSM sleep timer measures the duration of sleep time andwakes up the2G system upon the ending of sleep phase. Hardware calibration, erroranalysis, together with the low power and high accuracy concept of GSM sleep timerare elaborated in the paper.At last, the measurement result of the chip power consumption is presented in thepaper. When the2G system is in standby mode, the power saving ratio is89.8%compared with the situation without low power strategy. Analysis on the simulationwaveform of each feature verifies the low power concept and design requirements aremet as expected.