Bus Encoding Algorithm And The Power Dynamic Management

Historical perspective of developmental integrate circuit (IC) proves that power dissipation is a very important and difficult technical problem and also proves that power dissipation is motive power of IC technology alternation. It's why that the research to low power technique becomes much hotter direction.At present, mainstream semiconductor technology is complementary metal oxide semiconductor (CMOS). When no new technology is widely adopted, it is very significant to low power dissipation of CMOS IC. At the beginning of this paper, the source of CMOS power dissipation is described in detail and also its estimate is briefly given. Additionally, current low power techniques are introduced and classified by the view of design flow and design level.System on Chip (SoC) design has become well known. On-chip bus is its big part. To lower power dissipation of SoC bus and to keep away from the limitation of existing bus encoding technology in application field, two algorithms based on encoding are proposed for the existing bus specification. Taking account of the reuse characteristic of IPs and yet maintaining IPs function, decomposition bus-invert coding and zero-transition coding are both adopted to decrease transition rates of data lines and address lines for the first algorithm, decomposition bus-invert coding and gray coding for the second one. Results show that the algorithms significantly reduce power dissipation of chip-on bus and they're both effective and feasible for SoC bus.Dynamic management of power dissipation is another key research direction in SoC design field. Dynamic frequency scaling (DFS) and dynamic voltage scaling (DVS) are both attracting much more designers' eyes. With the project named Security SoC in Institute of VLSI Design of Zhejiang University, DFS has been considered and implemented. For next step reseach, the scheme of DVS is also proposed, and initially its simulation is well done.