Design And Verification Of Power Domain Control For UPC Subsystem Based On Baseband Chip

The rapid development of science and technology makes smart phones play an important role in people's lives,and people's demand for smart phone features has promoted the constant innovation of smart phone baseband chip technologies.However,with the integration of more powerful features on the chip,the complexity of the chip design is getting higher and higher,thus the difficulty of the chip design has been increasing exponentially and the power consumption is also getting more and more difficult to control,which have significantly restricted the further development of the baseband chip technology.Therefore,reducing chip power consumption and optimization system control of implementation of baseband chip have become the key areas in chip development and design,especially the design of the power supply control system,which is a particularly important aspect to be considered due to its direct correlation with dynamic power consumption.The content of this paper is based on a newly developed module,the Unified Processor Cluster(UPC)subsystem coming from part of a running Intel baseband chip project.The UPC subsystem is a multi-core subsystem targeted for high efficiency data processing as well as system level controlling.With the analysis of various functions provided by the UPC subsystem,the power domains of UPC subsystem are created rationally for different functions and the power demands.And based on the division method,the working principle of the related modules and the existing low-power techniques,the power control logic of the System Level Cache(SLC),which is in the ARC cluster of UPC subsystem,is systematically designed.On this basis,there are two different verification approaches used for the whole power domain control unit in UPC subsystem.One is with direct verification concept based on C language,which is used to verify the main functions of the power domain control unit directly and efficiently to improve verification efficiency and function coverage.The other approach sets up a verification environment based on Universal Verification Methodology(UVM)which is intended to apply random stimulus to detect bugs from deep-hidden corner cases and the ones that may have been missed from directed verification approach.In this way,the verification will be more complete and the results will be more accurate.The division of the power domain in UPC subsystem in this paper is based on a variety of low-power design methods,which make the consumption meet the design requirement.The power consumption indicator pre project requement is 120 m W,and the actual result is approximately 20 m W lower than the expected value.The power control design of the SLC control logic not only satisfies the requirements of the UPC subsystem functions,but also simplifies the logic by designing the state machine to control the power supply,the handshake between the state machines and controlling the state jumping by delay to make the control structure much more clear.In the aspect of verification,C language based direct verification guarantees a 100% function coverage for all of UPC power control logics.UVM based random verification makes the final code coverage reach 100%.The combination of two different verification methods makes the design meets all feature requirements.