Research On CDMA Module Test Based On SCAN

With the advancement of the production process and the ever-expanding chip scale,the test difficulty of the chip is gradually increasing.The traditional test method can not meet the test requirements of large-scale circuits,and the Design For testability has gradually become a popular test method.By adding a test circuit to the original circuit to achieve the test,although the chip area is increased,the test efficiency is greatly improved,and the test failure type is more abundant,and the test cost is also within the controllable range.The scan chain test is a test method in the Design For Testability.It is mainly tested for the internal logic circuit.By replacing the register with a memory cell with scanning function,it can be controlled by the test signal to generate test pattern.To achieve testing of various types of faults,this paper focuses on Stuck-at faults and Delay faults.In this paper,the CDMA module is taken as an example.The CDMA module is a sub-module in the baseband chip.It has about 110,000 registers.Through partial scan chain test method,how to make the CDMA module generate high quality test pattern under the condition of meeting certain test coverage requirements.To achieve this goal,it needs to involve some designs for test,including clock control,reset control,test compression,and hierarchical partition testing.These designs can increase test efficiency,reduce test time,and reduce test costs.The scan chain insertion is then implemented through the DC tool,mainly through script configuration.Later,using Mentor's Tessent tool to perform test vector generation of Stuck-at and Delay and obtain test coverage information,and to resolve DRC violations such as clock and data correlation,since the CDMA module belongs to the HAP module,it needs to be retargeted.The test pattern information thus obtained comes from the top layer and can be formally applied to the ATE device.Finally,build the timing simulation environment,read the SDF file,and use the VCS simulation tool to test the test pattern of the CDMA module separately for HAP and RET level timing simulation and ATE test,so as to improve the reliability of the test pattern and reduce the risk of tape out or tape in.Finally,the test coverage of Stuck-at faults of CDMA module is 97.67%,resulting in 7674 test patterns;the test coverage of Delay faults is 78.22%,resulting in 52353 test patterns,and the test patterns of the two fault types are verified by the timing simulation and ATE test.