The Design And Research Of Ultrahigh Speed Pipelined SAR ADC

Analog-to-Digital Converters(ADCs)can convert analog signals in our daily life to digital forms which are easier to store,process,and transmit,such as temperature,pressure,sound,and image.Thus,ADC are widely used in a variety of electronic products.Nowadays,with the development of mobile communication and mobile wireless networks.Electronic systems demand wider bandwidth ADCs.In portable electronics applications,there is a growing demand for ADCs with low power consumption.Therefore,it is meaningful to make research in high-speed and low-power-consumption ADCs.Communication systems,such as ultra-wideband radios,serial link and Ethernet transceivers,demand high-speed and medium-resolution ADCs with low power consumption.Making compare among different types of ADCs,Flash ADCs are the fastest,but waste a lot of power and acreage.Pipeline ADCs achieve both high resolution and high speed,but it still has high power consumption due to operational amplifiers between sub-ADCs.SAR ADCs have the advantage of low power consumption and high resolution,but its quantization speed is slow.Although the quantization speed can be improved by the time interleaving and its unique 2Bit/cycle technique,the speed is still insufficient with a few number of interleaving.Therefore,designing a high-speed,low-power-consumption ADC with a few number of interleaving becomes a critical challenge.In this paper,the 2Bit/cycle quantification scheme which is unique in SAR ADCs is analyzed in detail,as well as Pipelined SAR ADCs.A novel switching timing which is based on 2Bit/c for Pipelined SAR ADCs is presented in this paper.This new type of design avoids the charge leakage in the sampling switch with a half probability and relieves the original preset phase.It enhances the stability of the system greatly and improves the quantization speed of conventional Pipelined SAR ADC system by 100% and improves the quantization speed of conventional 2Bit/cycle switching timing by 12%.In addition,Some key circuits in the system are improved,such as the sampling switch,the comparator and the asynchronous timing module.Enhancing the stability and improving the quantization speed further.The non-ideal effects in the system are reduced with innovation methods.The prototype was fabricated in TSMC 65 nm CMOS technology.A 7-bit 2GS/s ultrahigh speed pipelined SAR ADC is presented with novel switching timing.The simulation results show that the ADC achieves 55.24 d B SFDR,43.45 d B SNDR and 6.92 Bit ENOB at sampling frequency of 2GS/s.