| PLL is a very important device of wireless transceivers. But the random fluctuations in the output phase of PLL is called timing jitter in the time domains and phase noise in the frequency domain. In the purpose of design a low phase noise frequency synthesizer, we design new components of PLL.In the systems, after analysis of the VCO phase noise generation mechanism and improving on the literature results, a design-oriented phase noise model for a complementary cross-coupled LC-VCO is provided. In the VCO,adopt a new a capacitor array structure, effectively reducing the voltage gain, thereby reducing the VCO phase noise, and the entire system phase noise reduction has important implications. In addition, through the introduction of capacitor array, but also increases the VCO tuning range, so that the scope of work of large VCO greater.In the charge pump, the full account of the advantages and disadvantages of the various charge pump, the charge pump in the non-ideal effects, charge leakage, charge mismatch conduct a detailed analysis, design a new structure of the charge pump.In the divider and PFD selection of the design were selected multi-mode divider and the structure of dead-zone PFD its greatly reduces system complexity and system noise. |
