Research And Implementation Of Ultrahigh Speed Transmission Physical Coding Sublayer

In recent years, internet traffic grows rapidly. The capacity of existing 100 G routers has almost been exhausted. Internet Service Providers(ISPs) have to expand the capacity of backbone devices in order to meet the internet traffic. Considering traffic growth and business development, a new platform with larger capacity should be a top priority for ISPs to expand the capacity, and ultrahigh speed transmission network should become the future trend.This paper is based on IEEE 802.3ba standard, and combined with OTN(Optical Transport Network) support characteristics proposed in IEEE 802.3bs. The PCS(Physical Coding Sublayer) over ultrahigh speed transmission network is designed and implemented in this paper.The related content of Ethernet is introduced firstly. Then followed a detailed study and analysis about the functions and key technical points in one of the multi-channel parallel 100 GE PCS. Finally, we focus on logic design, implementation, testing and simulation of the single 100 GE PCS sublayer.According to the MLD(Multi-lane Distribution) mechanism proposed in IEEE 802.3ba, PCS sublayer distributes data into multiple logic channels VL(Virtual Lane). Through different multiplexing methods, PCS adapts the data to different optical modules for transportation. This paper makes a detailed theoretical analysis about it. MLD mechanism is the key mechanism of 100 G Ethernet, which can be applied to higher-speed Ethernet transmission.Based on the mapping feature between Ethernet customer data and OTN, the 64B/66 B encoding and decoding modules of PCS sublayer in IEEE802.3ba are replaced by IFG insertion and IFG deletion modules. In this way, PCS sublayer can directly generate MAC(Media Access Control) frame data, which can be mapped into OTN frame, so that the data processing in 100G-transmission network can be simplified.The logic implementation in this paper is a part of a pre-researching project. The feasibility of replacing 64B/66 B encoding and decoding with IFG insertion and IFG deletion in ultrahigh speed transmission network is verified. VerilogHDL is compiled in Eclipse software to accomplish logic design of PCS sublayer functional modules. Modelsim is used to simulate. Vivado is used to synthesize, implemente, and generate a bitstream file. Then the bitstream is loaded into XC7VX690 T for testing and verifing. The result of simulation proves the correctness of logic design, and indicates that IFG insertion, IFG deletion, MLD mechanism are implemented successfully.