40nm PMOS Device Leakage Analysis And Yield Improvement

In recent decades,semiconductor technology has always developed to follow the Moore's law.The new technology not only improved the performance,area and power consumption of chips,but also promoted the continuous development of semiconductor industry and information industry.However,with the scaling down of device dimensions,emerging processing issues will also occur,such as a wider process deviation,longer interconnect delay,larger crosstalk noise and voltage drop,etc.All these effects worsen the yield rate.Thus,with a new process entering a mass production era,improving its yield becomes the toughest task,especially when the process technology is 40 nm or below.This paper mainly analyzed the mechanism of PMOS leakage defect under 40 nm process and put forward several methods to improve the yield.Defect analysis is always a big challenge for advanced process technology development.99% of process defects can be observed at the silicon surface via tools such as SEM.However,there is still a part of defects buried in the silicon,such as the PMOS leakage defects caused by contact CMP process.These defects will cause the failure of data retention.In this article,the voltage contrast(VC)inspection was adopted to detect the leakage defects during the process development of 40 nm CMOS.TheVC inspection found PMOS leakage by the improper implantation(IMP)of N+ source/drain(NP S/D),which would cause EOL yield loss by data retention soft bin failure.This is a process integration problem which involves the overlay performance of NP S/D photo,the critical dimension(CD)of the photo resist(PR)and the shrinkage of the PR by IMP process.The PMOS leakage was fixed by a series of process improvement actions,including the optimization of the optical proximity correct(OPC)for the NP photo mask,to re-target the CD and increase the PR hardness for NP lithography process.Instead of EOL CP test,the actions all can be inline verified by the VC inspection with large time advantage.The 40 nm process yield issue was finally solved.