An Integrated Circuit Yield Model For 40nm And 28nm Technology

As the high investment and high return characteristic of modern integrated circuit industry, the accuracy for project cost calculation from the company is becoming more and more important. The key value of a semiconductor design house is the IP they own, but how to transform the IP to the real money depends on the control and consideration of the cost management. The cost of the integrated circuit mainly located on the manufacture of the wafer, assembly and test. The yield of the wafer plays the key role in the return period of the project when it’s in the mass production. So in the plan of a investment, a good yield prediction is a must factor. However how to build a accurate yield mode, especially for the advanced technology is what the thesis discussed.The main part of the yield model is the possibility model, it is responsible for the yield loss which comes from random defect. The thesis compares the different possibility model, based on the real performance of the integrated circuit and integration in different technology, the poisson model is selected. There is also a correction based on the characteristic of the 40nm and 28nm technology node.The design of integrated circuit can’t live without EDA tools. In the calculation of the chip area, the area of advanced node chips doesn’t equal to the actual area. Only where it is sensitive to the defect is the effective area. The thesis uses the EDA tool CAA(Critical Area Analysis), do analysis based on different module and calculate the critical area, then uses poisson model and defect density to get the yield result.In the chip, memory size is always big, so the failure of the memory accounts for the most considerable part of the total yield loss. In the modern memory design, redundancy is always selected to improved the yield of memory. The yield model also should take the repair rate into consideration.Thesis combines the traditional possibility model, brings forward the problems which we encountered during calculating the yield of advanced technology. The solution to the problem is also included.Thesis also lists the example which uses CAA to analyze the yield.The model is corrected based on the comparison between the result of model calculation and actual yield.The model is used to calculate the yield of 40nm product. The gap between model and actual result is about 4%.The model is also used to calculate the yield of 28nm product. The gap between model and actual result is about 1%.