Gate-to-channel parasitic capacitance minimization and source-drain leakage evaluation in germanium PMOS

This work studies the behavior of both gate-to-channel capacitance ( CGC) and source-channel-drain/well leakage in metal-gate/high-kappa/Ge PMOS technology (W = 10 mum and L = 10; 5; 1 mum) under development at IMEC. The hole drift-mobility of germanium is ∼4X that of silicon, leading researchers to evaluate germanium as a possible channel material replacement for PMOS expected at the 32 nm technology node. In particular this study focuses on---but is not restricted to---(1) the presence of a parasitic gate-to-channel capacitance (CGC ), the large non-ideal trap assisted conductance which contributes to it, and its function versus Ge-PMOS architecture and gate length; (2) the existence of C-V tool compensation error due to CGC measurement technique resulting in conductance measurement error; (3) the presence of large source-channel-drain/well leakages characterized using a new MOS gated-diode measurement technique; (4) extrinsic capacitance (CEXT), flatband voltage (VFB), and effective oxide thickness (EOT) parameter extraction with discussion on inversion layer quantization.;This study found that excessive current leakages from the Ge-PMOS source-anddrain into the channel led to a chuck-dependent parasitic capacitance during CGC measurement. This excessive leakage is identified as a trap-assisted leakage through both AC and DC analysis. The chuck-dependent parasitic capacitance was an unexpected side effect of the PMOS architecture: namely the lack of N-Well isolation. The parasitic capacitance---dependent on both applied bias and frequency---was separated into two main capacitive components: a frequency-dependent source/well and drain/well trapassisted leakage capacitance (CPara_SD) and a frequency-voltage-dependent gate-induced junction leakage capacitance (CPara_GIJL). A third parasitic capacitance due to interface trap (IT) contribution (CIT) during channel depletion was also identified.;This study also found that the new MOS gated-diode measurement technique designed to separate and evaluate the source, channel, and drain leakage components is superior to typical VGS versus I DS methods when attempting to quantify the CGC measurement. The MOS gated-diode configuration allowed for temperature-dependent analysis and activation energy extraction ( EA), thereby providing a means to confirm individual leakage components: diffusion; Shockley-Read-Hall (SRH); trap-assisted leakage (TAL). TAL components include: Poole-Frenkel (PF); phonon-assisted tunneling (PAT); trap-to-band tunneling (TBT).;In conclusion, it was found that the source-channel-drain/well leakages and hence parasitic capacitances of PMOS built on relaxed germanium-on-silicon can be minimized by reducing the source/drain area, reducing the source/drain-to-gate contact distance, while increasing both the gate length and measurement frequency. The dominance of SRH and TAL during Ge-PMOS operation disagrees with diffusion dominance predicted by theory and as a result opens the door for future research. Future research includes Ge-PMOS fabrication on substrates free of dislocations---to minimize SRH and TAL current leakage contributions---so as to compare leakage performance.