Research On Yield Predicting Technique And Design For Yield

With VLSI entering the nanometer-scale era, the complexity of the manufacturing process grows explosively. The yield predicting technique and design-for-yield have become the research hot spots of VLSI industry. There is a direct correlation between yield and manufacturing cost. Yield predicting technique enables designers and manufacturers to estimate the yield and cost, and therefore avoids the risk of bringing design in low yield into manufacturing. Furthermore, under the guidance of yield predicting technique, designer and manufacturers can optimize the layout and the process. This thesis focuses on yield predicting technique and design-for-yield. It does research on the new problems brought by the new process and design flow, and also on how to handle these problems during the design stage. The following subjects are the summarization of the research contents and innovations:1) A yield-driven reticle floorplan software platform is implemented. we have done research works on how to take the yield loss caused by wafer dicing into consideration in reticle floorplan, and developed an yield-driven reticle floorplan software platform. This reticle floorplan software platform has been adopted by a foundry in mainland China.2) A yield-driven reticle floorplan algorithm considering both wafer dicing and random defect is proposed based on the platform. This algorithm takes the yield loss caused by random defect into consideration in addition. It avoids the further yield loss caused by wafer dicing for chip with low random defect yield. Compared with the algorithm considering only reticle area or the algorithm considering only wafer dicing, it reduces the number of wafers by15.22%or8.70%to meet the required quantities of all chips in a given MPW project.3) A yield-driven reticle floorplan algorithm based on position constraint is proposed based on the platform. By defining hierarchical groups of chips and introducing position penalty of chips in cost function, this algorithm eliminates the dicing conflicts between these chips and reduces the yield loss during wafer dicing. 4) An improved critical area extraction model for linear defect is proposed. The new planarization process generates a lot of linear defects. The yield predicting for linear defect relies on the corresponding critical area extraction model. The improved model takes the line end effect into consideration. It can be applied to general layout patterns for critical area extraction. It improves the accuracy of average critical area by16.90%for the sample layout with a lot of short lines. This improvement can provide more accurate feedback for DFY.5) A methodology of defect analysis and failure estimation for memory is proposed. The memory has dominated the yield of the chip. The redundant units for yield enhancement bring difficulty to the failure estimation of the memory. By means of this methodology, we can analyze the defect on-line and estimate if the memory is non-defective before electrical measurement. This methodology reduces time for testing. Because the problems can be detected in early manufacturing stage, it also reduces the manufacturing cost and project risk. This methodology has been adopted by a foundry in mainland China and is referenced in its patent.