Design And Implementation Of Dual-issue Microprocessor Based On RISC-V Architecture System

With the continuou,s development of embedded applications,the performance of embedded microprocessors has received wide attention.For some specific and efficient application scenarios,single-issue microprocessors have gradually become incompetent.At the same time,RISC-V has been widely adopted as an open source instruction set and with its unique advantages.Therefore,for the characteristics and problems of embedded applications,it is of great value and significance to develop a dual-issue microprocessor based on RISC-V architecture for embedded applications.Based on the analysis of the performance requirements of the embedded microprocessor,a sequential transmit dual-issue microprocessor is designed based on the RISC-V architecture and a six-stage pipeline structure.The microprocessor has branch prediction and cache.Support for the RV32IMF instruction set.The branch prediction uses the Gshare prediction scheme,and predicts two instructions every clock cycle,thereby reducing the branch prediction error rate;both the instruction cache and the data cache adopt the two-way group association mapping mode,and the replacement method adopts the least recently used replacement strategy.Data cache write operation uses write-back strategy,Cache organization mode effectively reduces the Cache miss rate,shortening the microprocessor's memory access time.The microprocessor uses an instruction queue to separate the fetch and the transmit,improving the processor's transmission efficiency.In addition,the microprocessor also includes two sets of execution units,wherein the multiply division and floating point arithmetic units are implemented in a multi-cycle manner,so that the microprocessor can perform correctly without affecting the overall operating frequency.Based on the dual-issue microprocessor architecture,the hardware implementation is implemented in System Verilog language,and its function is simulated.Then the performance of the microprocessor is tested by DMIPS,AES and other test procedures.The test results show that the dual emission micro-transmission The IPC of the processor is around 1,the branch prediction error rate is less than 10%,the instruction cache miss rate is less than 1%,and the data cache miss rate is less than 5%.Then the UMC 110nm process is used to synthesize the dual-issue microprocessor.The comprehensive results show that the processor has a maximum operating frequency of 142MHz and a cell area of 2.66mm2.Finally,the formal verification,physical implementation and post simulation of the design are carried out.