Design And Optimization Of X Microprocessor's Branch Prediction Circuit Structure

The application of pipeline technology has essentially improved the performance of microprocessor, it has become the basic characteristics of microprocessor. But the uncertainty of branch behavior about instruction stream, influences the performance of pipeline. The emergence of branch prediction technology can solve the problem to a great extent. Excellent branch prediction technology can effectively improve the efficiency of the instruction fetching, and become the basic guarantee of the performance improving. As a result, since 1990s, branch prediction technology has become the focus and difficult issue in the area of microprocessor.As to the static branch prediction technology, dynamic branch prediction technology can effectively adapt to the dynamic behavior of the program and predict the instruction stream more flexibly and accurately. In the current practical branch prediction technology, branch target buffer (BTB) is a common technique used in the branch prediction. According the record of the branch information, BTB can effectively predict the branch behavior and the target address of the latter instruction stream. Compared to other routine branch prediction technologies, BTB is more effective and easier to implement based on VLSI.Based on our in-depth analysis of the X microprocessor structure, this thesis proposed a four-bank and four-set structure BTB, comparing with multiple classical branch prediction technology. The method about allocation and replacement in BTB, lookup and update of the BTB entry, application of BTB branch prediction and dual RSB structure are involved in this thesis. We verify our design on the circuit module level and system level. As a result, the circuit which we designed can be used for the prediction of branch instruction. The validation of the test indicates that X microprocessor can work rightly. In addition, in order to fit the needs of the super pipeline and improve the accuracy of prediction further, we also complete the structural design of a BTB with 4K entries. The testing result of SPEC95 indicates that the miss rate of the BTB with 256 entries is 12.7%, while the BTB with 4K entries is 7.3%. Moreover, as for their prediction accuracy of branch instruction, both of them can reach 90%. By comparison, we found that increasing the volume of BTB to some extent can effectively decrease the miss rate and reduce the branch penalty of the pipeline, consequently improve the performance of the X microprocessor.