Design Of A 32-Bit Embedded RISC Microprocessor Based On FPGA

RISC has been rapid development since the last century, proposed in the mid-80’s. Particularly in the embedded field, almost all of today’s embedded microprocessor and most of the workstations and server vendors are using RISC architecture microprocessor. Since the 21st century, along with the SOPC technology’s appearance, Study on embedded microprocessor IP core with high versatility and flexibility also aroused great interest, and has been very widely used. Therefore, to study a RISC architecture microprocessor IP core based on FPGA has a significant application value.The paper first analyzes the single cycle processor microstructure, further design of the classic structure of five-stage pipeline microprocessors. Then analysis of the critical path pipeline, based on the structure of five-stage. Through analysis, identify bottlenecks which affect frequency performance, and re-divide of the classical structure of five lines.Then authors propose an optimization program, which has eight pipelined microprocessor architecture. and give excellent solution for pipeline hazard which is caused by increasing the pipeline stages.In solving pipeline control risk aspects, this paper presents a pipelined branch predictor. Relative to use the bubble or into the static branch predictor, dynamic predictor which introduced in this article has significant advantages in terms of flexibility and froexast accuracy. And because the pipeline structure, the logical components of the branch Predictor distributed in all the eight pipeline evenly. The benefits of this approach is that both to use the dynamic branch predictor to solve the problem of control risk, reduce microprocessor CPI, and does not make the logic of pipeline appear local congestion too reduce the frequency of the microprocessor. The design uses the Verilog language to describe the micro-processing system in the implementation stage. Then Functional simulation is carried out by simulation software-Modelsim. The single cycle, five-stage, six-stage and eight-stage architecture microprocessor are synthesized by synplify and static-timing analysised by ISE.The results verify the timing performance of eight-stage versions is better than the former three,And also higher than performance of the reference design in the domestic and foreign similar papers. Finally, through building hardware test system around the microprocessor, and verified on board. The eight-stage version is able to run at up to 146.62MHz on XC5VLX110T FPGA chip. So that this design realize a RISC flush type microprocessor soft core with an excellent performance.