Cache Prediction Technique

Based on the National Defense Preliminary Research Projects, the author have taken part in the research of 32bit embedded RISC microprocessor "LongTeng" R2, which is compatible to the Instruction Set Architecture (ISA) and the interfaces of PowerPC 750 of Motorola Inc.Cache is one of the most popular methods to solve the problem of the speed difference between the CPU and the Main Memory. The Cache prefetch is one of the prediction techniques, and it can improve the performance of cache effectively. This dissertation discusses the design, implementation and verification of Memory Management Unit and Cache, and the Cache has the prefetch function based on the research on the prefetch techniques.The research work of this dissertation mainly includes:1. Based on the architecture of PowerPC750, the dissertation have designed and implemented of memory subsystem, which includes 4 units of Instruction MMU, Data MMU, Instruction Cache and Data Cache. Based on the SMIC 0.18 um library and EDA place and route tools, the critical path of MMU and Cache is shorter than 4ns, which meets the demand of the whole microprocessor clock frequency of 233MHz.2. The dissertation studies the prefetch technique of Cache, and apply the prefetch function to Instruction Cache and Data Cache in "Long Teng"R2. The simulation result shows that the cache with prefetch gets the higher hit rate comparing with cache without prefetch function.3. By using Directed and Random verification methods, the dissertation implements simulation and verification to Memory subsystem in VERA, and get the desired code coverage and functional coverage.4. Under the FPGA simulation circumstance, "Long Teng" R2 successfully run some programs provided by the customer, including litter monitor program, big monitor program, float-point testing program and the BootROM program of VxWorks Operating System.The dissertation has contributed to the success of National Defense Preliminary Research Projects and the taping out of "Long Teng"R2 microprocessor.