Design And Implementation Of Branch Predictor For RISC-V

Recent years,the low accuracy of branch prediction has become a bottleneck restricting the further improvement of microprocessor performance,with the development of high-performance microprocessors towards the direction of ten or even twenty levels of deep water and wide emission.In general,the problem of low accuracy of branch prediction becomes more obvious in high performance and high frequency microprocessors.The low accuracy of branch prediction will lead to greater penalty delay of false prediction,and thus seriously reduce pipeline throughput and increase the extra power consumption on the wrong path.Therefore,it is of great significance and value to further improve the accuracy of branch prediction when designing high-performance microprocessors.The research in this paper is a part of RISC-V high performance secure processor chip project,focusing on the design and implementation of RISC-V branch predictor to improve the performance of processor branch prediction,reduce BTB collision failure,and improve the prediction accuracy of jump Target address and register related transfer instructions.The main research work and results of this paper are as follows.Firstly,the architecture of RISC-V instruction set and the characteristics of branch instruction are studied.Then,the conditions and the proportion of unconditional branch of the test set SPECint2006 used in the design are statistically analyzed to provide a basis for the branch types of the subsequent branch predictors.Secondly,BTB with hashed index is designed and implemented to solve the problems that affects the prediction of branch instruction,such as uneven hashing and collision failure,when the instructions are taken from 2 to 7 bit index in BTB.The relationship between the selection information of contrast tag,the length information of target address and the accuracy of branch prediction in this design is systematically studied.Based on a hash index method with minimum conflict and a BTB update method,the parameters and structure of BTB which primarily predicates execution component in high-performance processors,are determined.The BTB collision failure is reduced and the performance of branch prediction is improved.Next,in view of the difficult prediction problem caused by the correlation between the target address of part of the transfer instruction jump and the register,this paper 1).adopts the pre decoding multiple address weight record jump after the destination address method,2).designs and realizes a JALR(Jump and Link Register)instructions such as high accuracy of indirect predictor,3).studies and analyzes the key issues such as the design location and principle of the indirect predictor,so as to increase the prediction reliability of the target address of the jump and improve the prediction performance of BTB and the overall branch.Then,the prediction of jump direction is researched and designed.The prediction effect of branch instruction jump direction and the performance of supplementary predictor for jump direction is improved by using the method of two-bit counter preliminary prediction combined with TAGE predictor in BTB.Finally,pre-decoding and redirection logic of branch prediction are designed and implemented,and VCS simulation,DC logic synthesis and Formality verification are carried out for hash index BTB,indirect predictor,TAGE branch predictor,check and redirection and other logic.The results show that compared with the optimized processor,the overall performance of the designed processor can be improved by 2.82%.The prediction accuracy of BTB is increased by 3.24%.The prediction accuracy of indirect instructions is increased by 11.2%.The overall prediction accuracy is increased by 2.35%,and the frequency is increased by 2.22%,reaching the expected design goal.