Research & Development Of High Performance Embedded Media Processor IP Core

Rapid development of integrated chip techniques has driven the system design into System-on-Chip (SoC) age. Embedded media processors can accelerate the development of such systems and greatly reduce the development cost and system overall cost by intergrating media extension unit. Thus, the research and development of such processor IP cores has brought a lot of research attention. The author of this thesis attended the project supported by National 863 Program and the development of a media SoC namly MediaSoC, which is development by the SoC R&D Group of Zhejiang University. This thesis focuses on the R&D of an embedded media processor IP core (RISC32), which is integrated into MediaSoC as one of the programmable cores.This thesis consists of four charpters. The first charpter studies the classification and present research of existing media processing architecture and gives a detailed discussion of the importance of our research. The 2~nd, 3~rd, 4~th charpter are the main content of this thesis, mainly dicusssing three key problems in RISC32 development including multimedia instruction set extension design, processor pipeline micro-architecture optimization and other related problems which enable RISC32 to be a real IP core. The main contents and innovative points of this thesis can be summarized as follows: Based on the analysis of multimedia algorithms, this thesis dicusses the multimedia extension problem on a single-issue processor which is compatible to MIPS-I ISA. Then, we propose a general standard-cell based optimization process for processor datapath design.The proposed methods was applied to the multimedia extension unit development and the implementation demonstrates the superiority of our methods. In order to control the RISC+SIMD processor pipeline, this thesis presents a pipeline control strategry based on Finite State Machine (FSM) and a scalable super-pipeline structure of multimedia extension unit. To improve the pipeline frequency of the processor, we propose a special pipeline control structre which separate the signle centralized structre into paritial distributed control structure. Experiments show that our design could efficiently reduce the latency of pipeline control signals. This thesis presents a dynamical branch prediction structure in a sense of best performance-cost ratio by dynamical simulating. Experiments show that our structure can efficiently solve the control hazards, reduce the CPI of the processor and eliminate the unnecessary NOP instructions which are inserted to fill branch delay slot. Combined with the author's developing work of multimedia SoC(MediaSoC), this thesis dicusses other related problem on integrating the RISC32 IP core into this SoC.All the design methods were applied to develop the RISC32 IP core. As one of the two programmable processor cores, RISC32 was integrated into MediaSoC which is based on 0.18μm standard cell technology and taped out successfully. According to our experience, the IP-based MediaSoC system was very flexible and demonstrated to be a successful media processing approach with low developing cost.