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Microprocessor Dual-emission Technology Research

Posted on:2006-04-08Degree:MasterType:Thesis
Country:ChinaCandidate:L JiaFull Text:PDF
GTID:2208360152982168Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
Due to requirement for high speed information processing and complex intelligent control, the circuits with microprocessor as core are used wider and wider. Research and design in microprocessor architecture can promote the development of our national IC industry and satisfy market demand.The work in this thesis is part of National 05' project entitled "Application Specified high performance microprocessor (Long Teng R2)", NO. 41308010108. By studying RISC architecture and exploring design methodology, aim at design embedded 32 bits microprocessor compatible of PowerPC instruction.The embedded 32-bit microprocessor Long Teng R2 is compatible with instruction set and interface timing of PowerPC 750 microprocessor. The architecture is full copyrights. Using the Top-Down methodology, synthesis with SMIC 0.18um library, the clock cycle is less than 4ns. It also implemented on Altera EP1S80 FPGA and the third part applications have been successfully run on this Prototype processor.The research work of this dissertation mainly includes:1. Systematically analyze and research the high performance RISC microprocessor pipeline, design the "Long Teng R2" fix point pipeline, which is a 6 stages pipeline microprocessor.2. Design the microprocessor decode unit, propose the stepped decoder based on the instruction type. This method decrease the complexity of the instruction decoder debug, promote the design parallelism and easy for extend the function unit.3. Design the fix point pipeline controller。 To increase the clock frequency, to reduce area and power, design the pipeline controller based on the instruction execution cycle, which highly reduce the control path delay.4. Research the dual issue processor model performance at variable processor configration.5. Based on Long Teng R2 microprocessor pipeline, analyze the instruction decode and issue logic for dual issue embedded microprocessor. Propose the run time dispatched instruction decoder and issue logic based on instruction execution cycle.The dissertation work plays a great significance for studying the high performance microprocessors. The research work offers design considerations and technological reserves for further advanced microprocessor designs.
Keywords/Search Tags:superscalar, dual issue, embedded, issue logic
PDF Full Text Request
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