Modeling And Simulation Of Through-Silicon Vias In Si Interposers

2.5-dimensional integration technology refers to the stacking of active chips on passive devices,active chips and passive chips.A number of active IC are emitted to the passive dielectric layer.Because the silicon interlayer is passive silicon,there is no transistor in the middle,there is no TSV stress and heat dissipation.2.5-D integrated circuit is not only a transitional stage of three-dimensional integration technology,but also a very necessary process.Firstly,the background,significance and current status of three-dimensional integration technology and 2.5-dimensional integration technology are introduced,and the different shapes of silicon through-hole interconnection structures are analyzed.In this paper,the basic concepts of electromagnetic field theory and equation solution involved in the process of solving and modeling and simulation are sorted out.In this paper,a 2.5-dimensional integrated annular silicon through-hole pair and a silicon core annular coaxial silicon through-hole are modeled and simulated,including the analysis of electrical characteristics and signal integrity.The parameters of RLCG,impedance and admittance are calculated and extracted in Matlab software to obtain the MOS capacitance with non-linear variation.The equivalent circuit schematic diagram is simulated in ADS software and the model is simulated in HFSS software.Then the S parameters of the two simulation results are compared to verify the Correctness of the extraction parameters,equivalent circuit and model.