Parasitic Parameters And Equivalent Circuit Reasearch Of Through-Silicon Vias (TSVs)

With the unprecedented development of semiconductor technologies, the functionality and performance of Very-Large-Scale-Integration (VLSI) circuits have been promoted continuously. However, the semiconductor technology node is being aggressively shrunk to reach limits which are very difficult to supass, which has introduced lots of serious problems. The interconnect propagation delay and crosstalk have taken the place of the gate delay and become the dominant factor that determine the functionality and performance of the VLSI circuits. The through silicon via (TSV) technology have proven to be the critical enabler to realize a three dimensional (3D) gigscale system with higher performance but shorter interconnect length. It has the capacity to interconnect multiple design disciplines (Digital, Analog, RF, et, al.) by vertically stacking these chips on the top of each other. Therefore, the 3D IC could reduce the global interconnect length remarkablely, elevate the bandwidth and speed of signal transmission, increase the device integration density and utilization of the chip. Correspondingly, the propagation delay and kinds of crosstalk are also reduced prominently. These essential advanteges make the performance, volume and weight of 3D ICs far better than 2D Ics, which is the core development and technology of future ICs and System on Chip (SOC). In order to provide large scale of 3D systems, the theory design and manufacturing technology of 3D IC are very important. This paper researched the air-gap and air-cavity TSV, providing their parasitic parameters and equivalent circuits. The effects of high operating temperature and frequency are also included. The main studies of this paper are as follows:Ground-Signal-Ground type through-silicon vias (TSVs) exploiting air-gap as insulation layer are designed, analyzed and simulated for applications in millimeter wave. The parasitic capacitance of TSV can be approximated as the dielectric capacitance of air-gap, when the thickness of the air-gap is greater than 0.75 μm and the applied voltage to the TSV achieves flatband voltage. There is no need to indicate the threshold voltage, this is due to the small permittivity of air-gap. The proposed model shows good agreement with the measurements and simulation results of ADS and Ansoft’s HFSS over a wide frequency range of interest. The parasitic inductance of tapered ground-signal-ground (GSG) type through-silicon via (TSV) pair used in high speed three-dimensional integrated circuits (3-D ICs) are proposed. Rigorous closed-form formulas of the inductance, exploiting loop and partial inductances, are derived based on the geometric information with frequency up to 20 GHz, which also cover the cylinder and GS-mode TSVs. The proposed models are in good agreement with the 3-D electromagnetic (EM) simulator and measurement results with maximum errors of 8%. Besides with other parasitic parameters, the compact wideband equivalent-circuit model and passive elements (Resistance-Inductance-Conductance-Capacitance, RLGC) parameters are presented up to 20 GHz, with both design physical parameters. What is more, two kinds of equivalent-circuit models are proposed by our paper, due to the different thickness of air-gap, which make our models have better applicabilities.Based on the research of air-gap TSVs, a novel structure of low loss air-cavity through-silicon vias (TSVs) are proposed on normal low resistivity silicon (LRSi). The substrate coupling in high speed three-dimensional integrated circuits (3-D ICs) can be reduced by the air-cavity around the TSVs remarkably, which are assessed by the insertion loss and Q-factor. The air-cavity TSVs on LRSi are more efficient to promote the performance of TSVs than increasing the resistivity of silicon substrate. The accurate compact wideband equivalent circuit model and simplified π-model are derived based on the design physical parameters with frequency up to 20 GHz. Well agreements between the proposed models and full-wave simulation of Ansoft’s HFSS are shown over a wide frequency range of interest.The electrical performances of high-speed three dimensional integrated circuits (3-D ICs) are affected by temperature due to large integration densities, which may seriously affect the modeling and limit the reliability of circuits. The parasitic resistance of through-silicon via (TSV) including temperature effect is studied. With the consideration of skin effect, Temperature Coefficient of Resistance (TCR) is introduced to evaluate the sensitivity of TSV resistance to temperature changes. It can be found that the sensitivity of TSV resistance to temperature changes significantly both with the frequency and radius of TSV. The expression of TCR can be simplified to the one obtained by neglecting the skin effect, which shows better applicability.The received digital signal after transmission through a TSV channel, constituted by Redistribution Layers (RDLs), TSVs, and bumps, is degraded at a high data-rate due to the nonidealities of the channel. According to the range of operating frequency, two kinds of impedance matching technologies are proposed. When the operating frequency is 5 GHz, we incorporate an appropriate compact capacitance at the junction to mitigate the signal reflection with gigascale frequency. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. There are remarkable improvements of the quality of transmitting signals. When the operating frequency is in microwave range, the Chebyshev Multisection Transformers are proposed to reduce the signal reflection of TSV channel when operating frequency up to 20 GHz, by which S11 and S21 are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The RLGC elements of the TSV channel are iterated from S-parameters and the proposed method of weaken the signal reflection is verified by HFSS.