Signal Integrity Analysis And Electrically Modeling Of Through Silicon Via Connection In3D Integration

During the past decades, the trend in consumer electronics has been to develop products withbetter performance, smaller size, lower cost, and enhanced functionality. To keep up with theindustrial need, three-dimensional (3-D) integration is becoming necessary. In3-D integration systemor3D IC, through silicon via (TSV) is the core technology that provides a vertical interconnectionwith greatly reduced interconnection length among the stacked dies. The objective of this dissertationis to address high-speed signal-integrity issues which include signal attenuation and crosstalk amongTSVs in3D integration, and to electrically model TSVs as well as to study the MOS capacitanceeffect of TSV in3D integration.Firstly, based on the investigation of TSV integration and fabrication, we build a TSVinterconnection channel in a3D full wave simulator, and analyze the impact of physical and materialparameters on TSV electrical characteristics in details from frequency domain. During the analysis,we come up with some design guidelines with each parameter which is of great practical value.Secondly, we learn and study the theory of crosstalk, and make a deep research on the evaluation,suppression and modeling of TSV crosstalk from the below several aspects:1) based on the frequencydomain simulation and SPICE simulator, directly perceive and evaluate the impacts on crosstalk noiseof differential physical and material parameters;2) analyze the crosstalk noise under several aggressorTSV;3) study the impact on crosstalk of different TSV array bus. And the suppression measures fordesigning low crosstalk noise TSV interconnection channel are presented.Thirdly, we propose a high-frequency scalable electrical model of a via last TSV interconnectionchannel with bumps, which is based on the analytical RLGC equations derived from physicalconfigurations. Every component in this model represents a specific physical meaning. The accuracyand scalability of the proposed model is verified by simulation from the3-D field solver withparameter variation of TSV height.Finally, we study and analyze the TSV MOS capacitance effect in details. Based on the fulldepletion approximate (FDA) solution of depletion region, the equations to calculate the radius andcapacitance of inner and outer depletion region are presented. Parametric analysis of TSV capacitanceis performed on several physical and material parameters. Then, design guidelines are summarized forTSV used in signal and power delivery networks as well as for TSVs as variable capacitors.