Electrical Characteristics Study Of Tapered TSV Interconnectors On High Density3D-ICs

Through silicon via (TSV) is the key technology for high-densitythree-dimensional integrated circuits (3D-ICs) to achieve its shortconnections, small size, low power consumption, heterogeneous and otherkey performance advantages. However, TSV technology still faces manychallenges, establishing its equivalent circuit model and extracting itselectrical characteristics quickly and accurately is one of them. Commonlyused analysis method is simplifying TSV as a cylinder and analysis it withtransmission line theory. However, the inclination might be as large as20°in real TSV due to fabrication limitation, thus modeling and analysis ontapered TSV turn outs to be very necessary. The main works of this papercan be summarized as follows:First, this dissertation deduces the equivalent electrical characteristicsextracting method with return path in dual tapered TSV structure.Specifically, frequency-dependent resistance and inductance of dualtapered TSV are extracted from quasi-static Maxwell’s functions in goodconductor and current continuity equation in tapered structure. Depletionradius and MOS capacitance is solved from Laplace’s equation andPoisson equation. Impact of applied voltage and ambient temperature isalso given, and characteristics calculated in closed-form expression areverified with commercial software Q3D and HFSS, which shows goodagreement on the analytical results. Finally, improved Partial ElementEquivalent Circuit (PEEC) is proposed to calculate impedance of taperedTSV arrays. Results are also verified with Q3D. Second, analytical RLGC model is applied in driver-TSV-Load circuitto represent the signal response of pulse signal and trapezium signal withinverse Laplace Transform. Results show good agreement with HSPICEsimulation. Results also show that ignoring the RLGC model will leads toan error up to6.2%in delay and12.1%in rising time.