Research On Key Techniques Of Through-Silicon-Vias(TSVs) With Low Capacitance And High Interfacial Reliability

To meet the requirements for further development of through-silicon-vias?TSVs?with lower parasitic capacitance,higher thermo-mechanical reliability and smaller diameter but higher aspect-ratio,a novel process called“vacuum-assisted spin coating”,which combines conventional spin coating and vacuum treatment was proposed in this thesis for polymeric liner deposition along TSV sidewalls.Polyimide?PI?,which is compatible with standard CMOS process,was used as a representative polymer for the validation and optimization of the proposed technique.The wetting characteristics on bare silicon surface and shear thinning properties of polyamic acid solutions were both checked.Dielectric and electrical insulating properties of PI were also investigated.By utilizing the 4-inch silicon wafers with which blind holes with different geometric dimensions were formed beforehand,process optimizations were carried out by adjusting the viscosity of the polyamic acid solution,spinning speed,number of times of spin coating process.For blind holes with diameter of 8?m,depth of 120?m,aspect ratio as high as 15:1,PI liners with thickness around 500 nm were successfully deposited along via sidewalls with step coverage better than 33%.It saw a great improvement in uniformity considering that SiO₂ liners deposited by conventional plasma enhanced chemical vapor deposition process was with a step coverage around 10%.In addition,investigations on step coverage distributions of different samples which originally located in wafer center,middle of the radius and wafer edge validated the applicability of the technique into 8-inch silicon wafers.Based on optimizations of the processes for liner and seed layer sequential deposition for TSVs with small diameter and high aspect ratio,super conforming copper filling with no voids was achieved with high efficiency by utilizing commercially available electroplating chemistry while adjusting plating current density and total process time.By combining vacuum-assisted spin coating technique and super conforming bottom-up electroplating process,tapered blind silicon vias with open diameter of 6.8?m,bottom diameter of 4.5?m,depth of 54?m,aspect ratio of around 9:1,array size of 40×40 and corresponding yield of 99.5%were successfully fabricated.The C-V test results show that,at 25?,the accumulation capacitance and the minimum capacitance of one single TSV are 83.03 fF and 42.77 fF,respectively.The corresponding minimum capacitance density is 4.82 nF/cm²,which is half reduced compared with that of TSVs with SiO₂ liners.In addition,at 25?,leakage current between copper and silicon substrate of one single TSV was measured as 1.16 pA under bias voltage of 20 V.It was an order of magnitude smaller than that of TSVs with SiO₂ liners.While,at 125?,the corresponding value increases from 1.16 pA to 26.1 pA,and the leakage current density is0.13?A/cm² and 2.94?A/cm²,respectively.It changes to 0.27 pA and 0.23 pA after 30cycles and 60 cycles of thermal shock,respectively.The results indicate that stable leakage current property can be obtained after being subjected to 30 cycles of thermal shock for TSVs with PI liners.X-ray photoelectron spectroscopy?XPS?analysis showed that the PI liner formed was with an imidization degree of 92.8%.Energy dispersive spectroscopy?EDS?analyses validate the barrier ability of the formed PI liner in constraining thermal-induced copper diffusion.White light interferometer test results show that,after annealing under temperature of 350?for 1h,the pumping height of the central copper pillar relative to top silicon surface is 506 nm.It also shows that the pumping height increases with the annealing temperature.In addition,basing on the classic Laméequation,thermal stress distributions were firstly obtained,and then analytical solutions for the calculation of steady state energy release rate?ERR?along the two different interface were obtained by combining virtual crack closure and ERR criterion.The obtained analytical solutions considering impact of dielectric liners were validated by finite element analysis?FEA?.They were then utilized for the evaluation of impact of TSV diameter,type of liner material and thickness of liner on the interfacial reliability of TSVs.On the basis of the above,the product of the Young's modulus of liner and the square of its thermal expansion coefficient was proposed for the first time as the interfacial reliability criterion of TSVs,and the physical dimension design guides for TSVs with SiO₂/PI liner were also given.FEA simulation results also showed that,compared with the case of conventional SiO₂ liners,the equivalent von-Mises stress along each interfaces in TSVs can be reduced more than half by involving PI liners.It is expected to significantly enhance the interfacial reliability of TSVs by involving PI liners formed by vacuum-assisted spin coating technique.