Modeling And Simulation Of Through-Silicon Vias(TSV) For 3-D ICs

As the feature size of semiconductor devices is scaling down,the leakage current and thermal problems of transistors become more prominent.Moreover,the dimension of the on-chip interconnects has been steadily decreasing in the past decades,thereby leading to serious performance degradation and reliability issues.The time delay,coupling noise and power consumption of conventional copper wires are increased with the rapid development of semiconductor technology.To cope with them,it is necessary to develop three-dimensional integration to continue or even beyond the Moore's law.As a key technique of three-dimensional integrated circuits(3-D ICs),through-silicon via(TSV)has attracted much attention recently.TSV is a vertical conductor penetrating the silicon substrate,and it can enable the direct connection between devices of different stacking dies.With the implementation of TSVs,the interconnect length can be dramatically shortened.Therefore,the time delay,power consumption,and even the chip area can be reduced significantly.More importantly,heterogeneous integration of different functional blocks(e.g.,RFICs,memory,and MEMS)can be realized in one system by utilizing TSVs.In this thesis,the circuit modeling and parameter extraction of TSVs have been developed.The analysis of signal transmission performance and optimization have been carried out for TSVs.The thesis can be mainly divided into three parts:In the first part,carbon nanotube(CNT)was proposed as a new filling conductor for TSVs.The equivalent circuit model of CNT TSVs has been presented,with the concept of effective complex conductivity employed.The signal transmission performance of CNT TSVs has been captured and compared with their Cu counterpart.Moreover,it was experimentally found that the kinetic inductance of CNT may be much larger than its theoretical value,which results in significant performance instability in high frequency regime.In order to sustain performance,the composite of Cu and CNT was employed for building TSVs,and it was demonstrated that the implementation of Cu-CNT TSV can suppress the impact of kinetic inductance variation on the high frequency performance of TSVs.The second part was devoted to wideband modeling and parameter extraction for horizontal interconnects on re-distribution layer and differential TSVs.It has been demonstrated that the proposed equivalent circuit model can accurately predict the electrical performance of the horizontal interconnects and TSVs from DC to 100 GHz.Based on the proposed model,the impacts of design parameters and temperature on the electrical performance have been analyzed.The related will give beneficial references to the design and optimization of TSVs.The third part studied the parasitic capacitance of TSVs with the consideration of floating silicon substrate.A typical tri-TSV array in floating silicon substrate was taken as an example for crosstalk analysis.The equivalent circuit model was given,with the nonlinear capacitance effect taken into account.Also a coaxial TSV with floating inner silicon was studied.Based on the circuit model,transient voltage response of tri-TSV array and coaxial TSV were captured,with the parametric analysis performed.It was found that by introducing a certain oxide fixed charge,the parasitic capacitance of TSV can be sustained as a stable value in a range of voltages,which simplifies the modeling and simulation processes.In summary,this thesis makes some exploration on TSVs in 3-D ICs.The circuit modeling and characterization of TSVs are performed,and some beneficial conclusions are gained.