Design Of Low Power Instruction Cache

In embedded devices,Cache has covered the gap between microprocessor and main memory.But it also occupies a lot of power.Therefore,the low power design of Cache is more and more important.The instruction Cache has better temporal and space locality than the Data Cache and it has more optimization potential.This thesis only optimizes the instruction Cache.This thesis first introduces the composition and structure of instruction Cache.At the same time,the equations of energy,delay and energy delay product are analyzed.Also,the summaries of kinds of low power Cache design methods are showed.According to design flow of MCU(Micro Controller Unit)system,the analysis of instruction Cache in SystemC level is done.Through the mibench(code size greater than 10KB)test program,the change of energy delay product of instruction Cache under different configurations is showed.In the end,the proposed instruction Cache is implemented under the technology of smic 180 nm.The results show that for the whole storage system,the EDP is decreased by 26.936% and 93.68% compared with excuting code from SRAM(Static Random-Access Memory)and flash,which is better than the 11.621% and 60.559% of Ambiq apollo2.The optimizations of this thesis are as follows:1)Trigging Tag Cache and Data Cache on the rise and fall of the clock respectively.It combines the operation in phased Cache from two clock to one clock,avoiding the excessive sacrifice of timing.2)Adding the way prediction algorithm and modifying the implementation of the PLRU(Pseudo Least Recently Used)replacement strategy.The way prediction algorithm used PLRU register's value in order not to generate more power.3)In this reconfigure algorithm,the width of tag is modified so that the data in instruction Cache need not to be reset when configure changed.The advantage is that it avoids the time and power loss during the reconfiguration and increases the hit rate in some degree.