Analysis And Research Of Low Power Reconfigurable Cache In Embedded System

Several studies have shown that on-chip Cache memories account for about 50% of the total energy in modern microprocessors. Therefore, if we can reduce the power consumption of Cache access by changing its structure, power consumption of the processor chip can be effectively decreased. However, the relationship between Cache structure and system power consumption is quite complicated. Reduction of cache access power may increase off-chip memory access and finally increase the power consumption of the system. Therefore, the power consumption of the memory system should be evaluated systematically.In the thesis, we present the research on how to save energy at Cache architecture level.Our work starts with analyzing the key design elements of Cache, and selects 2 elements (capability and associativity) as the reconfig parameters according to the low power requirements. Then we define the structure of the reconfigurable Cache, set the reference system in which the Cache is working. Then we simulate the performance of the Cache. Based on the current studies about reconfigurable Cache, 3 types of reconfiguration methods are set, named static, segment and dynamic. In static method, suitable Cache configuration is selected by the pre-analysis of the application's characters, and the structure won't change during the programs running period; In segment method, cache configuration is changed at the predefined time in order to optimize the energy consumption of system more accurately; in dynamic method Cache's structure is automatically selected and changed by monitoring the application's behavior in run time.In order to analyze the optimizing effect, power modeling and evaluating standards are needed. In this thesis, the power of the memory system is divided into 3 parts: reconfigurable Cache, off-chip memory and CPU stall. Cache's power is modeled according to CACTI, a widely used Cache power and timing analysis tool.We evaluate and analyze the 3 reconfig methods roundly. To evaluate the efficiency, several standards are used such as average memory access power, energy delay product and unitary granularity parameter. To extract the useful data, calculate the parameters and draw graphics effectively, an automatic analyzing platform is built up, based on Perl, Shell and Matlab. Using this platform, the analyzing efficiency is increased greatly.In the study of dynamic reconfigure method, a unitary evaluating method is developed to help analyze the effect of granularity. Finally an appropriate granularity is gotten (3,000,000-5,000,000 instructions) in the reference system. If the reference system changes, the result may change. But the evaluating method and the platform can still be used to find the new appropriate granularity.Low-power embedded system development environment can be designed based on our reconfigurable cache hardware architecture and highly automated computation and analysis platform with little design cost while saving a lot of energy for appropriate application programs.