Research On Low Power Techniques Of The Instruction Fetching Unit In Embedded Processors

Low-power is the key researching aspect for embedded CPU while the power consumed by the instruction fetching unit contributes a great deal to the total CPU's power due to its numerous memory access. In this thesis we proposed several innovations on the low-power design of the most power-hungry components in instruction fetching unit and achieved significant power reduction while maintaining CPU's performance. The main content and innovations of the thesis include:1. Instruction link history based way prediction algorithm for low-power Cache design. We proposed a two-level branch way predication architecture consisted by a reused BTB and one branch link history table to resolve the problem of cacheline conflicts. By the method, we improved the accuracy of way prediction for branch pre-fetching and reduced the dynamic power of the instruction Cache while only cost little hardware resource.2. Loop access filtering based low-power branch target buffer. In order to reduce the power dissipation of BTB, we proposed a loop access filtering mechanism to eliminate the redundant BTB operation for sequential instructions in loops. Furthermore, we proposed a branch tracing method to compensate the performance penalty due to the over-filtering of the filtering mechanism for those non-loop branches. These two methods achieved magnificent power reduction for the BTB while only brought little performance loss.Techniques proposed in the thesis are based on simple architecture modification and little hardware cost and has some positive meanings to the low power design of embedded CPUs.