Research On Key Techniques Of Instruction Prefetch Unit Design In Embedded Processor

With the development of embedded applications, high performance and low power embedded processor will become the inevitable trend in the future. This thesis focused on the architecture design of the instruction prefetch unit in embedded processors. To improve the instruction prefetch performance and reduce the overall power consumption, we analyzed two important techniques for the implementation of instruction prefetch unit. The original contributions of this thesis are as follows:1. Based on the analysis of the overflow in multiple nested procedures, the wrong update under branch prediction and the prodedure return delay caused by instruction prefetch pipelining, this thesis illustrated the reasons and the impact of these problems, and proposed a zero-delay high-precision return address stack technology with the pointer-based correction mechanism. With the help of co-operation of the top pointer, the check pointer and the retire pointer, together with the trace for the procedure call and return on wrong predicted path offered by return stack backup, the method realized the correction and recovery to the return address stack. Application of this method in 32-bit high-performance embedded processor CK610 well met the needs of embedded applications and obtained higher prediction accuracy of procedure return instruction. Running Dhrystone benchmark program, the processor execution efficiency improved by 17.8%.2. To reduce the power dissipation of instruction cache, which is more significant in modern embedded processor, a low power instruction cache accessing method, based on inter-line linking history, was proposed. By creating configurable sequential and jumping linking table (SJLT), this method eliminated the inter-line accessing power of tag and redundant data memory. Moreover, a reusable linking status unit (LSU) was also created to solve the linking table flush and reconstruction problem caused by cache miss in traditional methods. Utilizing both SJLT and LSU effectively, significant reduction on dynamic power consumption was successfully achieved. Experiment showed that, in comparison with the traditional instruction cache, the novel method reduced 96.38% of the tag access with only 1.35% area increment of instruction fetch unit.Techniques proposed in this thesis had positive effects on performance and power of embedded processors.