Research On Power Optimization Of Cache Architecture Design

With the development of the IC manufacture technology and the functionality progress arising from microprocessors, the power issue is more seriously and becomes the main obstacle for improving the performance of microprocessors. Obvious power consumption will not only increase the manufacture cost, but also influence the microprocessor’s stability and credibility. On-chip cache consumes a significant amount of microprocessor’s energy. So designing an energy-efficient on-chip cache memory is the main object as feature size shrinks and capability and associativity of cache increase. Since circuit-level and logic-level low power technologies are highly influenced by the progress of process technology and material physical characteristic, they cannot meet the requirement of on-chip cache energy constrain. Architectural effort to reduce on-chip cache power consumption is considered.In this thesis, we proposed multiple power optimizations for on-chip cache architecture design based on the component of cache power consumption, the access characteristics of different cache and the balance of power and performance. The main contributions are as follows:1. Low power instruction cache design. Set-associative instruction caches consume a large potion of power in modern microprocessors. This paper analyzed the behavior of cache accessing and discovered that the most accesses were sequential accesses and short distance branches whose targets were to the adjacent cache line. So the paper proposed a new low power instruction cache architecture that recorded the link information of the current cache line and its adjacent cache lines. When a cache access occured, it could reuse the adjacent cache line links to get the way information of the target line. Then it could directly access one way of data array and avoid tag lookups to reduce the power consumption. When a cache line was evicted, only its adjacent cache line links should be checked and invalidated to keep the correctness of the links. 2. Low power data cache design. Data cache access with load-store-queue in parallel consumes a large amount of energy and in serial increases load-to-use latency. A low power data cache based on load-store-queue predicting access was proposed in this paper to filter out unnecessary access to data cache. Memory dependency set was defined to recode each load’s dependent loads and stores residing in load-store-queue. When a load instruction was fetched, its memory dependency set was checked. The load which only need access load-store-queue was decided and its result was gotten from the load-store-queue forwarding data-path, excluding to data cache access. As a result, data cache based on load-store-queue predicting access reduced power consumption without performance loss.3. Cache configuration algorithm. Configurable cache suffers the problem that the tuning interval does not closely match the phase changes of an application and high cost from configuration overhead. A subroutine calling based configuration prediction algorithm was proposed in this paper to improve the tuning interval and reduce the overhead. Since cache requirements might vary greatly across different subroutines, miss rate was checked when a subroutine was called. If miss rate overpast the threshold value, cache began to tune with the history optimization cache parameter of the subroutine. Furthermore, a cache line reuse mechanism between cache tuning was proposed by identifying the cache lines which belonged to pre-configuration or post-configuration to reduce the cache initial performance loss and power consumption.4. Reducing unnecessary access of instruction cache. According to the fact that branch prediction miss results in unnecessary access to instruction cache, a low power instruction cache based on a zero-delay branch prediction mechanism was proposed. Branch prediction behavior was used to predict the subsequent branches, which eliminated the branch history alias in deep pipeline and superscalar microprocessors. The accuracy of branch prediction was improved and cache unnecessary access power was reduced. Techniques proposed in this thesis can achieve aggressive power saving without performance reduction. Energy efficient of the microprocessor is also improved.